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Forums > Functional Verification > e

Subject: Virtual Sequences
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vlsi_dude
Posts: 55
Online: User is Offline
3/25/2008 5:08 AM  
I have two sequernces named x and y . i want first x sequence to generate data and at the receiver data checker determines the data as error free or not & then y sequence has to generate aknowledgement. So i created the virtual sequences and trying to control the x and y sequence driver individualy. but both the sequence start running at zero simulation time. wheather is it possible by using virtual sequences to take control over individual sequences. thanks and Regards, R.K
stephenh
Posts: 77
Online: User is Offline
3/25/2008 7:27 AM  
Have you tried overriding the default MAIN sequence in the x and y sequence drivers?
This is required if you want only the virtual sequence to control the sequences' execution.
extend MAIN x_sequence {
  body() @driver.clock is only {
    // do nothing
  };
};
Steve H.
er_gauravpatel
Posts: 4
Online: User is Offline
3/25/2008 9:31 AM  
You can disable the driving from the individual x and y sequence by following way and control both the sequence from the virtual sequence only.

<'
extend MAIN x_sequence {
keep count == 0;
};

extend MAIN y_sequence {
keep count == 0;
};

'>

Hope this will help...

--
Regards,
Gaurav Patel.
ASIC Engineer eInfochips.
www.einfochips.com
vlsi_dude
Posts: 55
Online: User is Offline
3/25/2008 9:41 PM  
Thanks dudes and let u know.

Regards,
R.K
thinkverification
Posts: 28
Online: User is Offline
3/25/2008 11:34 PM  
there's actually one more way to disable the lower level sequences...

extend my_sequence {
keep gen_and_start_main == FALSE;
};

:-)

Yaron
Yaron Ilani
VLSI Verification Specialist
www.ThinkVerification.com
vlsi_dude
Posts: 55
Online: User is Offline
3/26/2008 5:14 AM  
Hi all,

Thanks.Can you please solve this issue. while generating x and y sequences using virtual sequences, i'm facing problem.

sequences are not generated at all. will you please let me know how to make use of subdrivers with virtual sequences from the bellow code.

i'm pointing x_sequence driver to virtual sequence driver and same for y sequence.

This my env file. it as virtual sequence instance, tx_agent and rx_agent instance.
<'

extend env {

virt_driver : virtual_sequence_driver_u is instance;
keep virt_driver.env == me;
keep virt_driver.x_driver_u == tx_agent.tx_driver;
keep virt_driver.y_driver_u == rx_agent.rx_driver;

x_agent : tx_agent is instance;
keep x_agent.env == me;
keep x_agent.smp == smp;
keep x_agent.smd == smd;

y_agent : rx_agent is instance;
keep y_agent.env == me;
keep y_agent.smp == smp;
keep y_agent.smd == smd;


};

extend sys {

keep agent() == "Verilog";

env : env is instance;

setup() is also {

--set_config(simulation, enable_ports_unification, TRUE);
--set_config(gen, seed, random);
--set_config(run, tick_max, 10000, exit_on, error);
--set_config(run, tick_max, 5000);--, exit_on, normal_stop);
set_check("...", ERROR_CONTINUE);
--set_config(specsim, sync_reset, pre_run);
--set_config(cover, mode, on, auto_cover_events, TRUE);
};
};

'>


this is virtual sequence file
<'

sequence virtual_sequence using

created_kind = virtual_sequence_kind,
created_driver = virtual_sequence_driver_u;


'>


this is virtual sequence driver file
<'

extend virtual_sequence_driver_u {

env : env;
x_driver_u : tx_sequence_driver_u;
y_driver_u : rx_sequence_driver_u;

event clk is rise('clk') @sim;

};

'>


this my testcase, i'm disabled the individual sequences and then generating by using virtual sequences.
<'
import ../../../e/si_fw_top.e;

extend MAIN tx_sequence {

body()@driver.clock is only {
};

};

extend MAIN rx_sequence {

body()@driver.clock is only {
};

};

extend MAIN virtual_sequence {
!tx_seq_config : TX_SEQ tx_sequence;

!rx_seq_config : rx_sequence;


body()@driver.clock is only {

do tx_seq_config keeping {
.driver == driver.x_driver_u;

};

-- Wait for the event which indicate the data checking done and now to send responce.

do rx_seq_config;
};

};

extend tx_sequence_kind : [TX_SEQ]

extend TX_SEQ tx_sequence {

!tx_s : tx_data_components;

body()@ driver.clock is only {

do tx_s keeping {

...... };

};

};

'>

please corrct me.
thinkverification
Posts: 28
Online: User is Offline
3/27/2008 2:44 AM  
Hi,

I haven't had much time to look into this, but just a small thing I noticed is that the virtual driver clock is a dut signal.
I'd try to make it sys.any (event clock is only @sys.any).
I'll try to take a closer look later.

Yaron
Yaron Ilani
VLSI Verification Specialist
www.ThinkVerification.com
vlsi_dude
Posts: 55
Online: User is Offline
3/28/2008 5:18 AM  
Thanks. After changing the virtual sequnece driver clock according to subdrivers clock its working fine. And then i found that
virtual sequnece driver not pointed to subdrivers. so i made changes in tx and rx sequences. Now its virtual sequence environment working fine.

This what i changed in both the sequneces:
extend tx_sequence {

-- body()@driver.clock is only {
virt_d : virtual_sequence_driver_u;
keep soft virt_d == NULL;

-- };

};

extend rx_sequence {

virt_d : virtual_sequence_driver_u;
keep soft virt_d == NULL;

};

Thanks and Regards,
R.K
vlsi_dude
Posts: 55
Online: User is Offline
3/28/2008 5:18 AM  
Thanks yaron. After changing the virtual sequnece driver clock according to subdrivers clock its working fine. And then i found that
virtual sequnece driver not pointed to subdrivers. so i made changes in tx and rx sequences. Now its virtual sequence environment working fine.

This what i changed in both the sequneces:
extend tx_sequence {

-- body()@driver.clock is only {
virt_d : virtual_sequence_driver_u;
keep soft virt_d == NULL;

-- };

};

extend rx_sequence {

virt_d : virtual_sequence_driver_u;
keep soft virt_d == NULL;

};

Thanks and Regards,
R.K
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Forums > Functional Verification > e > Virtual Sequences


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