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Subject: delta delay issues...
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arjuny
Posts: 7
Online: User is Offline
4/03/2008 7:13 AM  
Hi,

    In my design i have two signals clock and data. the data(both are one bit signals). Data is changing exactly at the rise of the clock.
  
    In specman environment i am using the "@sim" to sample the clock.

   What value will be sampled by the specman at every rise of clock? (does it sample previous value or the updated value of data)


ddmello
Posts: 15
Online: User is Offline
4/03/2008 7:53 AM  
Hi Arjun,

If data is assigned using a blocking assignment (= in verilog), then you will see the new value in Specman. If it is assigned using a non-blocking assignment (<= in Verilog) then you see the old value (like other flops on the HDL side).

Please look atthe Specman docs, book: "Incisive® Enterprise Specman Elite® Testbench
Integrator's Guide Version 6.2" "9.5 Synchronizing with the Simulator (Callbacks)"

Hope this helps,
Dean
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