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Subject: eRM to OVM
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vlsi_dude
Posts: 55
Online: User is Offline
5/30/2008 3:32 AM  
Hi..... How to migrate from eRM to OVM? Somewhere I read it that we need SV interface (API) for accessing e components from SV environment. Can anybody tell me that whether we have to create that API or it is inbuilt. And whether those API are OVM complaint or not? Thanks!
mstellfox
Posts: 9
Online: User is Offline
6/08/2008 7:00 AM  
There is no need to "migrate" from eRM to OVM. OVM was built for multi-language support. Since there was not a good resue methodology for SystemVerilog, the first focus of OVM has been on delivering the SystemVerilog variant of OVM. You can think of eRM as the e version of OVM. In Cadence, we are working to ensure that eRM verification components can plug & play with SystemVerilog OVM verification components. That way, if you are an e customer, you can continue to enjoy the benefits of using e (since SystemVerilog brings nothing new to the table) and have the capability of sharing your Verification IP with others who might choose to use SystemVerilog. Of course, there are methodological implications for multi-language reuse. We can share what we have developed so far with you but it is probably better to do that with you directly vs. via this forum - especially since we are still in the early phases of developing this methodology. If you are interested to understand more details, I suggest you send me an email at stellfox@cadence.com.

Regards,
Mike
vlsi_dude
Posts: 55
Online: User is Offline
6/11/2008 4:16 AM  
Thanks Mike!

If I need more details then sure I will contact you at your email.
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