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Subject: "block based" sparse memory
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spadix
Posts: 1
Online: User is Offline
2/14/2007 2:46 PM  
This is another sparse memory model with an interface similar to shr_ram.  It attempts to improve performance by reaching a compromise between a flat implementation (used for fully/mostly implemented memories) and a keyed list implementation (used for very sparsely implemented memories) by using dynamically sized blocks to represent implemented regions.  See the user guide and examples for details.

Attachment: csco_blk_memory_version_1_0.tar.gz

parag123
Posts: 2
Online: User is Offline
7/11/2007 11:29 PM  
Is there something similar available in System Verilog also.
If yes, could you pprovide a example

Regards,
Parag
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Forums > Functional Verification > Shared code - e Files > "block based" sparse memory


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