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Subject: e-code: DLX VLIW modeling and test generation
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Posts: 157
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2/05/2006 12:20 PM  
This shareware package contains an environment for functional test
generation for a modified version of the VLIW DLX architecture
using Verisity Specman Elite.

The implementation is a modified version of the DLX architecture. It has five stages: Fetch, Decode, Execute, Memory, and Writeback. The Execute stage has four parallel paths: integer ALU, four-stage floating-point adder(FADD), seven-stage multiplier (MUL), and a multi-cycle divider (DIV).

Please see more details in the package README file.

This shareware was contributed by Prabhat Mishra, University of California, Irvine. The work was supported by the Verisity University Program.

Author: Yaron Kashai updated 5/10/2004 42163 bytes

Attachment: vliwDLX.tar.gz
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Forums > Functional Verification > Shared code - e Files > e-code: DLX VLIW modeling and test generation


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