- VSE needs to hire a contractor to meet a peak staffing need to complete Duarte on schedule. - Duarte is a validation silicon design used to validate PCI-Express Gen2. The design is used internally for validation of server chipset products.

We need a talented individual to complete implementation of cell-based design (CBD) FUBs from synthesis thru post-layout verification and tapeout. In this position, you will be working closely with other CBD designers to develop the custom recipes for the synthesis and Auto-Place and Route (APR) tools to implement the design. You will run static timing analysis on your FUBs to verify they meet project targets.

Completion of several Application Specific Integrated Circuit (ASIC) designs is preferred. Additional qualifications include:

- Unique mix of software and circuit design skills

- Excel at root causing tool and/or flow problems and automating the fixes and/or workarounds

Must have experience doing convergence work for several years in the We are looking more for folks that have been doing convergence work for several years in Cadence First Encounter tool suite.

Additionally, MUST have experience in most of the following areas:

- Physical synthesis / SoC Encounter

- Clock Tree Synthesis / SoC Encounter

- Routing / SoC Encounter

- Static Timing Analysis and convergence / Primetime

- DRC/LVS verification flows

- Formal Verification

- Good scripting and programming skills

- Willing to consider this experience on Physical Compiler, Apollo, Astro, and/or Magma only if experience on SoC Encounter knowledge can't be found.

- Synthesis / Design Compiler

- Floorplanning / SoC Encounter

- Noise analysis and convergence / Celtic

- EM/SH/IRDrop analysis / VoltageStorm-