the answer to your question depends on many parameters of your design and design-kit. If you have only one digital block, it is straight forward to import it into Virtuoso: In Encounter you need to generate GDS, verilog without physical instances for simulation and verilog with physical instances for verification. In Virtuoso AMS-simulator you can easily tell to use the simulation_only verilog files for full-chip simulation and the imported layout_verification verilog files should provide a 1 to 1 match for layout vs schematic testing. We use this flow regularly for the purpose you mentioned

However, there might be pitfalls.
- Things get very different, depending on whether your digital designkit provides full standart-cell layouts or abstracts only. You may find it difficult to tell the LVS how to identify abstracts... Easy way out: make an LVS dummy of the digital part with analog transistors inside, which connect to the top level ports of the cell. After verification, replace the dummy by the acctual digital part.
- You may need a layer-mapping file at streamout from Encounter, to make the layers of the digital part appear right in the Virtuoso layout.
- Alternatively you could use LEF/DEF or OA to exchange data, but this is for recent versions of the software only, and has some flaws as well, if your digital and analog design kit use different layer names...

In general, your approach seems fine to me and you can definitely get it to work that way. You might need some tweaks here and there -- if your designkit is cool, it might just work without any hassle. I do it the same way and keep doing it :-)

If you have any doubts, dont hesitate to post again. I would appreciate to hear about your progress when you get there.

Cheers, Joachim