Tuesday, February 07, 2012     Register | Login | Search | Contact Us
     
   
     
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
Home
Forums
Forums > Cadence Academic Network > RF Methodology

Subject: RF Design flow when implementing an inductor
Posting to forums is available to community members only.
Login or Register
Rate this topic:
   
Author Messages
paulo.trevisan
Posts: 2
Online: User is Offline
5/09/2008 4:27 PM  
HI

What is the best design flow when I want to implement an inductor on chip using Cadence Tools?

Thanks
jrascher
Posts: 2
Online: User is Offline
5/15/2008 3:38 AM  
Hi Paulo,

i would recommend the VPCD-Tool, in long Virtuoso Passive Component Designer. You will need an assura technology file.

Hope that helps,
Jochen
paulo.trevisan
Posts: 2
Online: User is Offline
5/16/2008 11:08 AM  
Ok Jrascher, thanks. I will look up this option.

By the way, is it possible to extract the inductance of an onchip inductor with Assura HF? Could I consider this extraction as a net which represent the inductance of my inductor or it just extract the parasitics substrate and I should not consider this as an equivalent model of my inductor?

Thanks
HansH
Posts: 1
Online: User is Offline
6/03/2008 11:58 PM  
Hi Paulo,

We have used the following flow:

1) Do the initial inductor layout using VPCD (Virtuoso Passive Component Designer)
1a) Select proper tech files, substrate conductivity and layer purposes
1b) Choose target values for the inductor --> get initial geometry parameters
1c) Finetune the geometry parameters manually for optimal performance (keep the DRC rules in mind)
1d) Generate layout

2) Fix by hand the layout generated by VPCD to comply with the DRC rules. (The automatically generated layout may have missing layers or ports etc.)

3) Use a proper EM-Solver (like Virtuoso RF-Designer) to verify the parameters of the fixed layout.

Here is a paper that may be helpful when fine tuning the geometrical parameters:

C.B. Sia et al. "Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications,"
IEEE Transactions on Electron Devices, vol. 52, no. 12 (December 2005), pp. 2559-2567.

BR,
Hans
Posting to forums is available to community members only.
Login or Register
Forums > Cadence Academic Network > RF Methodology > RF Design flow when implementing an inductor


ActiveForums 3.6
     
Copyright 2006 Cadence Design Systems, Inc.