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paulo.trevisan
Posts: 2
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| 5/09/2008 4:27 PM |
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HI
What is the best design flow when I want to implement an inductor on chip using Cadence Tools?
Thanks
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jrascher
Posts: 2
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| 5/15/2008 3:38 AM |
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Hi Paulo,
i would recommend the VPCD-Tool, in long Virtuoso Passive Component Designer. You will need an assura technology file.
Hope that helps,
Jochen |
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paulo.trevisan
Posts: 2
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| 5/16/2008 11:08 AM |
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Ok Jrascher, thanks. I will look up this option.
By the way, is it possible to extract the inductance of an onchip inductor with Assura HF? Could I consider this extraction as a net which represent the inductance of my inductor or it just extract the parasitics substrate and I should not consider this as an equivalent model of my inductor?
Thanks
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HansH
Posts: 1
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| 6/03/2008 11:58 PM |
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Hi Paulo,
We have used the following flow:
1) Do the initial inductor layout using VPCD (Virtuoso Passive Component Designer)
1a) Select proper tech files, substrate conductivity and layer purposes
1b) Choose target values for the inductor --> get initial geometry parameters
1c) Finetune the geometry parameters manually for optimal performance (keep the DRC rules in mind)
1d) Generate layout
2) Fix by hand the layout generated by VPCD to comply with the DRC rules. (The automatically generated layout may have missing layers or ports etc.)
3) Use a proper EM-Solver (like Virtuoso RF-Designer) to verify the parameters of the fixed layout.
Here is a paper that may be helpful when fine tuning the geometrical parameters:
C.B. Sia et al. "Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications,"
IEEE Transactions on Electron Devices, vol. 52, no. 12 (December 2005), pp. 2559-2567.
BR,
Hans
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