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Forums > Digital IC > Formal verification

Subject: Black Box Mismatches
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saikiran_454
Posts: 2
Online: User is Offline
5/30/2008 3:47 PM  
Hello Everyone,
      I have problem with the black box matching.
      I am trying to run a LEC on top level(RTL to gates) by assuming the core blocks are black boxes. Other than these black boxes top level have the JTAG, PINMUXING, PAD, clkrst and some clock blocks. I am seeing black box non equivalences. I tried to diagonise one of the black box which has a feedback to its input from its own output, i found that the outputs ports from which the feedback has to come is different in both the RTL and Revised when checked in the schematics, but i checked the connections in both RTL and Revised netlist and i have found that they are connected properly coming from same port.
            I have found that all other black boxes are unequal because one of its input are connected to the other black box outputs, and all these ports are mismatched between RTL and revised in schematics, but in RTL and netlist theyare correctly connected, so LEC is assuming the different port? why?

Example:   to explain the scenerio
  testblock1 and testblock2 are blackboxes

  testblock1 :                                                         testblock2:
      blockoutΒ:0]  (5bit output bus)                          blockinputΏ:0]

     blockoutΑ:2] are connected to blockinputΏ:0] in both revised and RTL. testblock1 is non equivalent black box and if we diagonise testblock2. The input port blockinputΎ] is connected to the blockoutΐ] in RTL and blockoutΒ] in Revised. Can i know y this is happening in LEC? If the black boxes are non equivalent then y it is assuming these. What are the basic checking does LEC do to see whether black boxes are equal.

         
Please also find the basic do file used.
system mkdir -p lec
set analyze option -auto
set log file lec/lec.log -replace
date
set UNDefined Cell black_box -both
$read_LIBRARY
$readRTL
$readNETLIST
add pin constraints 1 vddmem -both
  add pin constraints 1 vddp -both
  add pin constraints 0 vss -both
  add pin constraints 0 vsso -both
  add pin constraints 0 vsspll -both
  add pin constraints 0 jtag_trst_l -both
set flatten model -seq_constant -seq_constant_x_to 0
//set flatten model -seq_merge
set flatten model -nodff_to_dlat_zero
set flatten model -nodff_to_dlat_feedback
set flatten model -latch_transparent
set undriven signal 0 -both
report black box
set mapping method -name only -nosensitive
set system mode lec
set mapping method -name first
map key points
add compared points -all
compare
exit -force


Thanku,
Sai.





 

 
   
     
broesicke
Posts: 2
Online: User is Offline
6/13/2008 8:31 AM  
By default lec will assume that the bus is defined in ascending order, but it looks like you are defining the bus in descending order. Try adding the -noascend switch to the set_undefined_cell command.
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Forums > Digital IC > Formal verification > Black Box Mismatches


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