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Naderi Posts: 33 Online:
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| 7/04/2008 5:16 PM |
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| Hi all
I need to connect the power pads to power pins (vdd, gnd) in the design, and I am using following commands for that:
>>globalNetConnect gnd -type pgpin -pin DUMMY -inst ioco_vssioco_1 -module {} -verbose
>>globalNetConnect vdd -type pgpin -pin DUMMY -inst ioco_vddioco_1 -module {} -verbose
which, DUMMY is the pin name defined in the reference vss_pad in the library.
however, First Encounter (v4.1) issues following errors and warrnings, and doesn't work:
**WARN: No PG pin 'DUMMY' in instances with basename 'ioco_vssioco_1' in the design.
**ERROR: No PG pin 'DUMMY' in any cell in the LEF files.
**WARN: No PG pin 'DUMMY' in instances with basename 'ioco_vddioco_1' in the design.
**ERROR: No PG pin 'DUMMY' in any cell in the LEF files.
**WARN: Floating InOut term DUMMY of Io inst ioco_vssioco_1.
**WARN: Floating InOut term DUMMY of Io inst ioco_vddioco_1.
Could someone help me please?
Thanks,
Ali
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BobD Posts: 80 Online:
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| 7/07/2008 9:48 AM |
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It sounds like you're trying to operate on a single IO instance rather than many instances in the design and the tool is getting confused because it is expecting to string match the instance names. Perhaps you could try the following syntax:
globalNetConnect vdd -type pgpin -pin DUMMY -singleInstance ioco_vddioco_1 -verbose
Please do post back and advise whether this resolves your problem.
Thanks, Bob
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Naderi Posts: 33 Online:
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| 7/07/2008 10:42 AM |
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Hi Bob Thanks for your answer.
I used your command and following is a part of log file.
0 new PG-pin connection was made to global net 'vdd'. 0 new PG-pin connection was made to global net 'gnd'.
**WARN: Floating InOut term DUMMY of Io inst ioco_vssioco_1. **WARN: Floating InOut term DUMMY of Io inst ioco_vddioco_1.
and in the layout, Encounter didn't connect the pin to the pad.
1- I am a bit surprised of using "-singleInstance" switch, because this switch is not given in manual (v4.1) for globalNetConnect command. 2- Regarding the warning message, which complains for Floating InOut term, maybe the error is due to definition of the DUMMY pin in the pad. Is there any type other pgpin for IO pins? Or any other solution?
Thanks, Ali |
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Naderi Posts: 33 Online:
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| 7/09/2008 8:32 AM |
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This is a part of pin definition in reference LEF file for my GND pad. (In its schematic DUMMY is used as the only pin)
PIN DUMMY DIRECTION INOUT ; PORT LAYER M1 ; RECT 29.730 143.360 29.910 143.920 ; END END DUMMY
It is supposed the DUMMY pin be connected to the gnd net by Encounter (which encounter v4.1 can not find the DUMMY pin as a pgpin).
Can someone tell me wheather it should include "USE" and "SHAPE" statements? because I see all other gnd/power pins contain these two statements. example: > USE GROUND ; > SHAPE FEEDTHRU ;
Thanks, Ali
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BobD Posts: 80 Online:
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| 7/09/2008 9:04 AM |
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Hi Ali,
I did some testing trying to user globalNetConnect to connect a signal pin to global power/ground nets. I'm seeing that globalNetConnect will not work unless that pin has a "USE GROUND" or "USE POWER" statement that aligns with the polarity of the global net you're trying to connect it to.
Hope this helps, Bob
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Naderi Posts: 33 Online:
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| 7/09/2008 9:36 AM |
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Thanks a lot Bob,
If you don't mind, I have another question. If a pad is a regular IO and is used for let say "clock" pin or "reset" pin, then, how should it be introduced to the Encounter? How "globalNetConnect" can find it to connect to associated net in the layout? Which command is usable?
Thanks, Ali
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BobD Posts: 80 Online:
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| 7/09/2008 10:51 AM |
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globalNetConnect is intended to be used by nets defined in your config file as power or ground nets. These nets are typically not in the Verilog netlist.
Nets like clock and reset are typically in the imported Verilog netlist and are not considered "global" nets. Their connections to the pins on the IO cells are typically made in a top level Verilog netlist that instantiate the core module and completes the connections between the core IO module pins and the pins on the IO cells. How to best create this import Verilog netlist varies depending on the tools you have at your disposal, but if you're interested in doing this task within FE it is theoretically possible using Interactive ECO commands like "attachTerm" and "attachModulePort". After executing these commands and creating the connections, saveDesign should write out a netlist that had the pins on the IO cells connected.
-Bob
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Naderi Posts: 33 Online:
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| 7/09/2008 1:50 PM |
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Great, I really need to learn this part of flow. Therefore, connecting a POWER PAD to a layout, in a case that PAD pin is a regular IO and is not a pgpin, should be done by Interative ECO commands in FE. I looked in libraries and couldn't find any pad with the pgpin-type pin. Isn't it easier/common to instantiate all pads including IO and power earlier in design flow, perhaps in the synthesis time?
Merci, Ali |
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BobD Posts: 80 Online:
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| 7/09/2008 1:57 PM |
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| I agree it is indeed common to instantiate the pads and their connections if possible at an earlier stage in the design flow. |
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bougantp Posts: 19 Online:
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| 7/10/2008 1:12 AM |
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I am sorry guys, if you are discussing about STMicro Libraries, the famous DUMMY pin of each IO should be connect to gnd through the FE netlist (This is consider as a logical Pin and not a PG pin).
Pat. |
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Kari Posts: 81 Online:
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| 7/14/2008 7:48 AM |
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If all the IO pads are not in the netlist out of synthesis, and the clock/reset/etc pins are not already connected, then I would consider that an incomplete netlist and ask for a new one!
- Kari |
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Naderi Posts: 33 Online:
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| 7/14/2008 8:56 AM |
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Hi Pat.,
Yes, I am using STMicro. But the DUMMY pin is not in my IO pads. I have DUMMY as the only connection for a VDD or VSS pad, which should be connected to VDD or GND. The instance names in cmos90nm tech. are :
IO90GPHVT_BASIC_50A_7M2T/VDDIOCO_LIN IO90GPHVT_BASIC_50A_7M2T/VSSIOCO_LIN
DUMMY pin is defined as an in-out pin and not a pgpin in the LEF file , maybe becasue there are some ESD circuitery in the cell. Such definition prevent the FE to connect DUMMY pin to the global VDD or GND nets.
As Kari and Bob mentioned, these power pads may require to be instantiated like other IO pads earlier in the RTL. However, what command do you use in FE to connect a non-pgpin-type pin (i.e DUMMY pin) to a global net like GND?
Thanks all your comments, Regards, Ali
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Naderi Posts: 33 Online:
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| 7/14/2008 8:57 AM |
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Hi Pat.,
Yes, I am using STMicro. But the DUMMY pin is not in my IO pads. I have DUMMY as the only connection for a VDD or VSS pad, which should be connected to VDD or GND. The instance names in cmos90nm tech. are :
IO90GPHVT_BASIC_50A_7M2T/VDDIOCO_LIN IO90GPHVT_BASIC_50A_7M2T/VSSIOCO_LIN
DUMMY pin is defined as an in-out pin and not a pgpin in the LEF file , maybe becasue there are some ESD circuitery in the cell. Such definition prevent the FE to connect DUMMY pin to the global VDD or GND nets.
As Kari and Bob mentioned, these power pads may require to be instantiated like other IO pads earlier in the RTL. However, what command do you use in FE to connect a non-pgpin-type pin (i.e DUMMY pin) to a global net like GND?
Thanks all for your comments, Regards, Ali
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Kari Posts: 81 Online:
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| 7/15/2008 2:38 PM |
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If the DUMMY pin is *meant* to be a pg-pin, I would hack the LEF to say USE POWER/GROUND. However, if the LEF is bad then the vendor really should fix it, so this is NOT a blanket-recommendation to edit LEF files. If the DUMMY pin is just meant to be tied low, then the verilog netlist should have it connected to 1'b0.
- Kari |
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