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Topics Started By Replies Views Last Post Posting Code to the Forum Administrator 3 3083 by croy 5/30/2008 1:14 PM Introducing your forum Moderator, Dave Goldberg Administrator 0 3087 3/07/2006 9:38 AM Using the Forums Moderator 0 2320 1/20/2006 12:18 PM LEC Hier-compare when sub modules have extra port in Revised Design!! chirag 3 371 by croy 7/14/2008 3:55 PM Black Box Mismatches saikiran_454 1 466 by broesicke 6/13/2008 8:32 AM Regarding sample dofile for in lec verify mode sreenivasaraov 4 1521 by sreenivasaraov 5/14/2008 6:43 AM lint warning waiver jowu 2 2329 by oopsrk 5/12/2008 5:54 AM waive mapped points jowu 1 767 by croy 5/09/2008 6:38 PM Not-mapped help yepp_hjs 1 677 by croy 5/09/2008 6:35 PM Clock gating cosifan 1 1121 by croy 4/15/2008 5:19 AM How to trace flops with constant inputs in Conformal? cosifan 1 824 by croy 4/15/2008 5:17 AM RTL vs. gate netlist verification mapping problem alihusaini 1 2142 by croy 3/17/2008 9:18 AM Unmapped point (extra) sreenivasaraov 1 957 by croy 3/17/2008 9:15 AM inverted equivalent points sujittikekar1 1 1181 by croy 3/17/2008 9:13 AM help needed sujittikekar1 1 957 by croy 3/17/2008 8:31 AM Non-equivalences due to different device. caddina 1 1260 by croy 3/17/2008 8:22 AM Unmapped point (not-mapped) issue sreenivasaraov 3 2404 by jessican 3/03/2008 6:53 PM verilog .v lib vs synopsis .lib jowu 1 1453 by croy 3/03/2008 3:12 PM Conformal struggles to resolve abort points (due to complex logic) cheksan 3 2851 by makkarm 2/09/2008 7:52 PM poor performance of LEC compile -parallel tom.tseng 1 2930 by makkarm 12/15/2007 9:06 AM
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