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Administrator 2 2485
by adbeckett
2/18/2008 12:06 AM
Iintroducing your forum moderator, Anna Votino (amvotino)
Administrator 0 2452
3/30/2006 9:29 AM
Using the Forum
Moderator 0 2300
1/20/2006 12:23 PM
Hierarchical Design Flow
arunrach 0 41
7/01/2008 4:57 PM
Hierarchical Design Flow
arunrach 0 20
7/01/2008 4:57 PM
SOC Encounter ICFB Mismatch
arunrach 0 21
7/01/2008 4:53 PM
LVS + no connect pin
jgrant3 0 69
6/23/2008 3:22 AM
Net_nwell net_welltap DRC error
jgrant3 2 88
by jgrant3
6/19/2008 3:24 AM
Diva errors.
prahladh 6 517
by adbeckett
5/23/2008 6:22 AM
Resistor label/pin problem
jgrant3 1 286
by jgrant3
5/19/2008 6:00 AM
Drawing circles in Virtuoso
jgrant3 5 522
by jgrant3
5/19/2008 12:46 AM
DRC error AMTS maximum MTOP spacing
jgrant3 1 297
by adbeckett
5/15/2008 6:50 AM
how to autofill a layout ??!
isazul 1 853
by sagirameshraju
5/09/2008 6:06 AM
layout density check with Diva.
isazul 0 604
4/14/2008 7:09 AM
parasitic resistance extract minimum value
isazul 0 682
4/09/2008 9:13 AM
Exporting Hspice netlist file.
Azme 0 896
3/19/2008 8:21 PM
LVS out of swap memory
wochiang 2 1550
by wochiang
3/16/2008 11:55 PM
LVS error for Dummy MOS
isazul 4 1535
by adbeckett
3/13/2008 12:27 AM
LVS Matching error
isazul 3 1843
by adbeckett
3/05/2008 9:26 AM
how to calculate the total routed wire length?
iandanur 1 1902
by Devi
2/19/2008 12:47 AM
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