Friday, January 09, 2009     Register | Login | Search | Contact Us
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
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Topics Started By Replies Views Last Post
Visit the new Cadence community
host 0 204
8/02/2008 9:07 AM
This forum is now read only
host 0 866
8/02/2008 9:07 AM
PSL endpoints and ended()
weberrm 12 2883
by jmueller
10/10/2006 6:26 AM
for/generate
Administrator 9 6934
by TAM
8/23/2007 11:21 AM
Psl assertions for checking ECC
abna 9 7653
by darrowchu
9/14/2007 12:10 AM
interdependent constraints
rajendraorpe 8 2245
by rajendraorpe
7/12/2007 7:46 AM
Check if req has ever happened before ack
Thomas666 7 6038
by Thomas666
9/03/2007 4:43 AM
IFV Regresssion
jent 7 7639
by jent
11/01/2007 7:40 AM
Can I force or probe a signal in vhdl module from verilog top testbench?
foster 6 5918
by ccc
5/08/2007 9:04 AM
Property for when writes to a fifo stop
weberrm 6 2795
by cbeaureg
2/23/2007 6:50 AM
Verilog model of PSL
weberrm 5 2593
by ckomar
10/19/2006 10:50 AM
modeling a constraint for a signal that is only high once (ever)
ssa 5 2481
by ssa
11/15/2006 5:16 PM
Using the Forum
Moderator 5 2610
by Administrator
2/20/2007 5:04 PM
PSL Assertion
vlsi_dude 5 4576
by jmueller
7/12/2007 2:12 AM
forml verification on system level verification
abna 5 3657
by stephenh
1/16/2008 10:05 AM
how to aggregate tests and results
e_vangelist 4 1647
by e_vangelist
4/14/2008 5:50 AM
Searching for PSL packages
gregorypoirier 4 4868
by ajeetha
8/02/2007 9:22 AM
Keep internal signals' names after synthesis
mvetromille 4 4709
by ajeetha
11/22/2007 7:01 PM
Auxiliary code:Tick event not synthesiseable
Thomas666 3 7332
by Sibil
9/18/2007 9:48 AM
How to tackle 'Aborted' properties.
bijitm 3 3458
by ssa
5/08/2007 8:28 AM
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