Friday, November 21, 2008     Register | Login | Search | Contact Us
     

Many of you already received communications about the move of the Cadence user community into cadence.com. And many of you have already joined, with over 4000 registrations in the first two weeks.

The new Cadence Community enhances the ability of Cadence users to connect and collaborate. In addition to moving the community into cadence.com -- enabling single sign-on for community, Sourcelink and Cadence events -- the new site is organized around nine technology segments, giving you easy access to product information, training, forums and blogs. Some of the new features include:
  • Ability to respond to posts via e-mail
  • Technology-specific blogs
  • Latest Web 2.0 social networking capabilities
  • Public profile options
  • Private messaging
  • Friends lists
Visit the new Cadence Community today at www.cadence.com/community and join the discussions!

Registration note: Due to the scope of the enhancements and the new SSO registration system, we were not able to migrate existing cdnusers.org member accounts. So new registrations are required, but this enables a broader set of functionality we think you'll enjoy.

Forum note: Under the guidance of forum moderators, we have taken the 20+ cdnusers.org forums and consolidated them into 11 forums on the new site. Posts have been brought over so you can leverage that posting history. CDNusers forums will be set to read only starting 7/30, and cdnusers.org will be redirected to the new community on 8/4.

Best regards,
Mike and Tom

Michael A. Catrambone - Steering Committee Chairman
Distinguished Engineer
PCB/Mechanical
UTStarcom, Inc.

Tom Diederich
Cadence Community Manager
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Topics Started By Replies Views Last Post
New Functional Verification forum on the new Cadence Community
host 0 318
7/13/2008 4:09 PM
This forum is now read only
host 0 669
8/02/2008 9:09 AM
Constraints, randomize bits in a vector
ross.weber@unisys.com 3 2744
by tpylant
1/27/2006 12:11 PM
System Verilog ... for dummies
marco.stanzani 6 4465
by stellfox@cadence.com
4/19/2006 6:58 AM
Parameterized classes
weberrm 1 2522
by weberrm
5/04/2006 7:51 AM
Introducing Your Forum Moderator, Nitin Sharma (nitin_sharma)
Administrator 0 3356
5/24/2006 4:47 PM
Be sure your ideas are part of the Top Care-about Survey report
Administrator 1 2377
by christinechen
6/20/2006 7:02 PM
serial transmission of structures
marco.stanzani 1 2399
by kameade
7/21/2006 11:16 AM
ncsim for System Verilog
prasad_vc 2 3003
by prasad_vc
9/20/2006 1:58 AM
Need help regarding interface usage in Systemverilog...
prabhuk 1 2325
by tpylant
9/20/2006 9:29 AM
DPI Example
prasad_vc 0 2490
9/21/2006 2:18 AM
Using Artisan standard cells in Verilog??
student1 0 2241
11/23/2006 7:31 AM
Poor SystemVerilog Support in NC?
chm 6 2638
by nitin_sharma
12/01/2006 4:44 AM
SV DPI: veriusertfs
bennik 5 3048
by bennik
12/11/2006 12:22 AM
What is wrong with this code ? I'm trying to use a Queue of classes..
mirzani 2 2179
by mirzani
12/14/2006 5:23 AM
Clocking Block assignment bug in IUS583?
davyzhu 2 2835
by stephenh
12/20/2006 4:57 AM
Three new SystemVerilog EZ-Start appnotes and code examples
Adam.Sherer 1 2652
by mblake
1/04/2007 6:01 AM
Creating fifo channel between class objects
mirzani 1 3206
by tpylant
1/04/2007 12:40 PM
compile SystemVerilog and Verilog separately?
davyzhu 8 3216
by davyzhu
1/09/2007 10:27 PM
uRM task-level interface?
davyzhu 3 2809
by davyzhu
1/11/2007 5:25 PM
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