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Topics Started By Replies Views Last Post Introducing your Forum Moderator Administrator 0 2209 7/27/2007 4:51 PM [CAN] University of Erlangen-Nuremberg jrascher 0 237 5/15/2008 4:49 AM [CAN] FEEC BUT Brno CZ, Dept. of Microelectronics description prokopr 0 516 4/18/2008 7:51 AM [CAN] POLITEHNICA University of Bucharest claus61 0 1718 11/19/2007 7:43 AM [CAN] RWTH Aachen University sjoeres 0 2380 9/13/2007 11:03 PM [CAN lead] Technical University of Ilmenau and IMMS pteichmann 0 1989 9/10/2007 5:19 AM [CAN] Department of Microelectronics and Computer Science, Technical University of Lodz gwj 0 2722 8/31/2007 11:09 AM [CAN] AGH University of Science and Technology szczygie 0 1739 8/31/2007 8:34 AM [CAN lead] University of Mannheim skapferer 0 2161 8/14/2007 5:07 AM [CAN lead] University of Freiburg (Albert-Ludwigs-Universität-Freiburg) jmbeck 0 2251 8/06/2007 6:00 AM BETA PHASE phaspel 0 2176 7/31/2007 12:09 PM
Posting to forums is available to community members only. Login or Register  Forums > Cadence Academic Network > Cadence Academic Network Member List	Special Topics --Low power --Design Data Management Digital IC --Synthesis and test --Formal verification --Floorplanning, Place and route Custom IC -- Custom IC Electrical Design -- Custom IC Physical Design --Shared code - SKILL Silicon-package-board --Signal Integrity and Modeling --PCB Design -- IC Package, SiP and Co-design --Shared code - SKILL Functional Verification --Simulation, Acceleration, Emulation --Assertion-Based Verification and Formal Analysis --SystemVerilog --Verification Planning --<i>e</i> --Shared code - <i>e</i> Files Cadence Academic Network --AMS Methodology --RF Methodology --Verification Methodology --Cadence Academic Network Member List --Cadence Academic Network Announcements --Cadence Academic Network Event Notices --Cadence Academic Network General Questions General topics --Suggestions --Event Notices --Jobs

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