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Interview: Turbo Technology Speeds Analog Simulation, Preserves Accuracy

April 28, 2008, Michael Tian - Cadence Design Systems

Cadence® Virtuoso® Multi-Mode Simulation 7.0 was released on April 10, 2008. cdnusers talked to Michael Tian, engineering director of the Virtuoso Spectre R&D teamRead more »
Interview: Key Features in Virtuoso 6.13 Release

April 28, 2008, Steve Lewis - Cadence Design Systems

The Virtuoso 6.1.3 release integrates the Cadence Space-based Router into the Virtuoso cockpit to help users work more easily with sub-90nm design.Read more »
Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems

April 28, 2008, Keith Felton - Cadence Design Systems

Today’s designs require flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments.Read more »
Getting Plastered

April 16, 2008, Dr Alison Burdett - Toumaz Technology Ltd

Toumaz Technology has developed Sensium, an ultra low power wireless sensor interface and transceiver platform for a digital plaster style application that allows for remote real-time health care monitoringRead more »
Interview: Verification Planning and Management Methodology Focuses on All the Right Things

March 24, 2008, Ze'ev Shtadler - Cadence Design Systems

Verification Planning and Management is rapidly becoming accepted as an important technical discipline for advanced designs.Read more »
Challenges in Implementing DDR3 Memory Interface on PCB Systems

March 17 2008, Phil Murray - Altera Corporation

Covers modeling, simulation, and physical layout approaches required to meet JEDEC-defined termination and tight timing requirments for designing DDR3 memory interfaces on PCB systemsRead more »
Why Care About Power?

March 12, 2008, Dan Shlomi - ARC

A series of presentations from Cadence Low Power SeminarRead more »
Parallel and Modular Flows over a Basic Chip Level Environment

March 11, 2008, Shlomi Sperber - Texas Instruments, Israel

Discusses Parallel and Modular flows used in making various productsRead more »
Low-Power Methodologies in a Multi-Core Networking Chip

March 10, 2008, Udupi Harisharan - Cisco Systems

Illustrates the low-power techniques applied on Cisco's ASIC to optimize the clock-tree power including clock gating, clock layout (First Encounter technology), and low-power flop circuitryRead more »
Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure

March 5, 2008, Narayanan Thondugulam - P.A. Semi

Describes the use of Cadence Chip Optimizer for design closure in conjunction with SoC Encounter GXL-based place-and-route flowsRead more »
Model-Based Verification and Analysis for 65/45nm Physical Design

February 27, 2008, Jason Hibbeler - IBM

IBM and Cadence are developing a software infrastructure combining MRD checking and yield simulation, allowing for flexible integration of different (including third-party) simulatorsRead more »
Cadence Signal Integrity for Double Data Rate Interface

February 13, 2008, Prithi Ramakrishnan - Motorola

Discusses the use of Allegro PCB SI in the design and analysis of a processor-memory interface in one of Motorola's products.Read more »
More news »

Congratulations

Pilar Hsue from National Semiconductor, and Hank Sun from AMD were the winners in the Nintendo Wii drawing for completing their IC Packaging and Functional Verification Top Care-about surveys.

Thanks to the many participants who completed a survey this year to provide feedback to Cadence.


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