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 | |  | | | | | Interview: 45 nm and Below: Analyzing New Dimensions
An interview with Vassilios Gerousis, Digital IC Technologist
Cadence Design Systems | |
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As designers and process engineers delve into 45 nm process technology, they find the landscape more unforgiving than ever, margins of error tighter. Vassilios Gerousis, Cadence Digital IC technologist, works with users who are already deep in the trenches of new design technology. We asked him to talk to us about what’s going on at the 45-nm level.
cdnusers: What areas of IC design are you working on?
Vassilios: I work on advanced IC design to address 45 nm and below. I focus on design challenges in areas such as sign-off analysis, statistical design, and litho-aware design.
cdnusers: What new effects do designers have to account for at 45 nm?
Vassilios: There are many effects that are becoming first order in 45 nm. Sign-off analysis is an area of concern, taking variations into account. Manufacturing effects, such as litho, CMP and stress, are more prominent in 45 nm designs than they have been at 65 nm or above. These effects have more impact on the variation for leakage as well as timing.
We see more thermal variation at 45 nm. Going into small geometries gives you the advantage of being able to have more gates on a chip, but more gates generate more heat and, as a result, each portion of the chip can operate at a different temperature rather than having a uniform temperature as is modeled today.
cdnusers: You mentioned analysis. Is traditional sign-off analysis running out of steam at smaller geometries?
Vassilios:Yes, I think it is starting to run out of steam because as we shrink the technology, the silicon nodes, we get larger designs. And, as we shrink geometries, we need to look at process variations—process variability can impact design performance and predictability. At 45 nm, runtime and capacity increase the complexity of timing analysis, in terms of both performance (runtime) and memory. On top of that, we have to figure out how to address silicon variations efficiently.
Unfortunately, the traditional corner-based approach does not address variations in an efficient way. Corner-based analysis is focused at the extreme points of the process parameters and considers all parameters to move in the same direction. It does not address the variations of process parameters when they move in different directions, which can, eventually, result in over design or even in chip failure. To address process parameters correctly would require an extremely large number of corners to be generated and analyzed.
cdnusers: What are you talking about when you talk about variations?
Vassilios: Variability can be defined in terms of how things can move away from the nominal manufacturing conditions. The variations around nominal conditions can be classified as random or systematics. Random variation is modeled and analyzed in a statistical way. Systematic variation, like litho or stress, is analyzed using model-based techniques, i.e. manufacturing models.
In essence, we can model delays and leakage as a function of these variations. Designers can predict with confidence how a chip would perform under these process variations. For advanced designers, the move to a statistical design methodology can help in predicting and optimizing his/her design while considering both random and systematic variations. That’s why at advanced process technologies, we are moving to Statistical Static Timing Analysis.
cdnusers: What is Statistical Static Timing Analysis?
Vassilios: To talk about Statistical Static Timing Analysis or SSTA, I will talk about it in comparison to Static Timing Analysis or STA. In STA, you are propagating the deterministic delay values, and with SSTA you are propagating the nominal value with variation around the nominal value as a function of process parameters. SSTA applies statistical formulas to propagate statistical delays to obtain the final results, like slack. The final result is the statistical distribution of slack, arrival time, or any timing checks like set-up or hold time. SSTA can also predict the timing yield of a design. How many chips can be manufactured with the slack value that you have identified?
cdnusers: Can you talk more about the differences between STA and SSTA?
Vassilios: SSTA is a new concept for designers, primarily because most of the analysis tools—the ones designers are used to—are not statistical in nature. With STA, you get a single value for clock frequency or arrival time. But, with SSTA you get, for example, a statistical distribution of path arrival time. We offer designers the ability to do timing analysis and optimization with a selected number of sigmas. For example, SSTA provides sign-off based on the mean plus 3 sigma. The n-sigma sign-off approach of SSTA improves design margins in comparison to corner-based sign-off.
cdnusers: So, does SSTA replace STA?
Vassilios: Right now, SSTA enhances STA. For some time, I believe both of them will need to be used.
cdnusers: Why?
Vassilios: STA is used in the front-end portion of the design. SSTA will be used for sign-off and physical optimization. As designers gain more confidence, they will start to migrate SSTA to front-end design portions.
cdnusers: If we are using SSTA through the design flow, do all the tools along the design flow have to be SSTA aware?
Vassilios: Yes, eventually. We are looking at how we can make tools SSTA aware in terms of optimization and sign-off. We are trying to move the process forward in the design flow so, in the future, we can predict variability while we are doing placement as well as prototyping. Right now the major effort is to be able to get the n-sigma sign-off to be silicon proven—comparing SSTA results with actual silicon and seeing how the two are correlated.
cdnusers: Who is using SSTA today?
Vassilios: Advanced users, specifically those going to new technology nodes. Engineers see SSTA is a “must have” for 45 nm technology. We are working with several customers who are using SSTA in advanced technologies—at the sign-off stage as well as the optimization stage.
cdnusers: What do you see as the major benefit of SSTA over STA?
Vassilios: In STA, I get one single number that is going to tell me if I pass or fail. In SSTA, I get timing results as a distribution. What is the benefit of having these distribution numbers instead of just a yes or no? Essentially, SSTA models delays as a function of those critical parameters in the manufacturing process. What the distribution allows you to do is to specify exactly which magnitudes of variation you would like to sign off to. For example, you can sign-off at 1 sigma of the distribution, you can sign off at 2 sigma distribution, and you can sign off at 3 sigma distribution. So, it gives you additional data—you have the flexibility to decide at which point to sign-off, rather than always signing-off at the worst case, which is what people do today.
cdnusers: What are key considerations in choosing a SSTA tool?
Vassilios: I would say integration, modeling—the ability to create accurate models—and statistical optimization, the ability to optimize the design by digging into process variations that have been analyzed by SSTA.
cdnusers: When will we begin seeing SSTA driven tape-outs?
Vassilios: I think we will see tape-outs sometime next year.
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About the author
Prior to joining Cadence Design Systems Inc., Vassilios Gerousis, Digital IC Technologist, worked at Texas Instruments, Motorola (Freescale) and Infineon Technology in the area of design implementation and analysis. He currently focuses on advanced IC design to address 32 nm and 22 nm technologies such as statistical design, litho-aware design and package-aware design. Vassilios holds a master’s degree and doctorate degree from Northeastern University.
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