| |
|
|
 |
| |
 | |  | | | | | Cadence Low-Power Methodology Kit Automates Area, Timing, and Power Exploration
An interview with Amjad Qureshi, Digital Kits Architect
Cadence Design Systems | |
| |  | |  |
At CDNLive! EMEA, Cadence introduced its Low-Power Methodology Kit. The Kit brings together a comprehensive low-power methodology, best practices, and codified flows—all demonstrated and proven on a wireless segment representative design containing leading Cadence and third-party IP. The Kit is highly modularized, providing a holistic methodology covering logic design, verification and implementation.
cdnusers interviewed the Low-Power Methodology Kit architect Amjad Qureshi to find out what the Kit contains, how it works, what it does for designers, and why this Kit is important to designers facing the complex challenges of low power design.
cdnusers: Tell us a little about your background prior to joining Cadence as a Kit architect.
Amjad: I joined Cadence about 14 months ago. Before that, I spent more than 18 years in digital design management, as well as working hands-on in many design roles. At my last job, a start-up, I was the director of engineering, developing a multi-dsp, multi-core SoC. I created the entire design team: architecture team, front end design, and implementation as well as chip bring-up teams. Prior to that, I worked for several large corporations developing and implementing several SoC designs ranging from 2 microns, back in the old days, to recent 65 nanometer designs.
cdnusers: So you really have some insight into challenges in the industry today. How did that help you in the development of the Cadence Low-Power Methodology Kit? What role did you play in the development of the Kit?
Amjad: Basically defining the entire flow. As an architect, I defined the entire segment representative design based on a low-power wireless application. From that definition came these critical flows that are addressing today’s complex, real designs and low-power challenges. Defining the requirement included processor selection, memory selection and third party IP, and designing with internal Cadence blocks such as the power control module, and putting the whole infastructure and platform together to ensure it addresses the challenging low-power design needs.
cdnusers: For the day-to-day digital designer, how is the Low-Power Methodoloty Kit going to help them get their job done with the least amount of stress?
Amjad: The Kit is actually quite broad—addressing all digital design phases. It deals with multiple clocks, multiple power domains, global signals, third-party IP, and libraries, so understanding the overall block-, chip-, and system-level requirements from the architectural level is one of the key benefits of the Low-Power Methodology Kit. Usually power is an afterthought and not considered seriously in the architectural or front-end design phase. That complicates the implementation of the physical design and verification phases and eventually causes either a major schedule slip or chip re-spin. With this Kit, the front end design team, the verification team, as well as the physical implementation team, all communicate with each other and understand the power along with the architects (both the system and chip architects) using the Common Power Format (CPF).
cdnusers: What exactly is the Low-Power Methodology Kit, what are the pieces?
Amjad: Basically, the Kit addresses every phase within the design cycle. We are not teaching people how to design an SoC. We're helping them address low-power issues in flows for each phase of the overall design process.
Within the kit are:
- Methodology based flows
- Demonstrated on a segment representative design
- Combined with verification partner IP
- Delivered with applicability consulting, which allows the customer to customize the flows to their design environment
We offer an entire workshop that comes with user guides, methodology guides, as well as white papers, and product guides. The Kits R&D team has developed extensive and comprehensive micro-architecture specs highlighting and documenting each of the flows. The Low-Power Methodology Kit in particular describes how to address low-power challenges in any SoC design.
We are really addressing the entire digital design scope. We broke it into flows since not all customers will want all the flows. For example, many customers outsource the back-end, so they would only be interested in the front-end flows.
cdnusers: What is the one key feature designers should know about this Kit?
Amjad: There is not one key feature—each flow comes with a key feature of its own. In most designs, power, timing, and area are all overlapping and potentially conflicting, and they need to be in balance. Some people address power, timing, and area in the beginning, but we need to balance all three throughout the design.
There are many features in the Kit that are considered key. The design phases in the Kit are:
- Design creation—logic synthesis
- Formal implementation and verification using Encounter Conformal Low Power
- Functional and formal verification using Incisive verification technologies
- Physical design, or back end, focusing on timing closure, place and route, and signal integrity using the SoC Encounter system
- Design for testability
- Power-grid sign off
Each of these phases comes with many key features addressed by the Low-Power Methodology Kit. There are basic power techniques, which include clock gating, multi-threshold, and multi-Vt, as well as more advanced techniques such as power shut-off and multi-supply voltage, addressed throughout the Kit.
cdnusers: How does the Kit align with the recently announced Cadence Low-Power Solution?
Amjad: The Kit uses the Cadence low-power methodology—we have created a Common Power Format (CPF) file throughout the 6 flows utilizing the latest features from each product. We also used a single file throughout the Kit; the representative design in the Kit is a real-world design. We spent a lot of time in the beginning to make sure this design is really representative.
cdnusers: What do you see as the “big” challenges facing digital design teams in low-power design?
Amjad:The challenges, as I would list them, are:
- Aggressive power requirements—today’s designs are becoming more and more complicated and the processes are shrinking
- Moving from single-core to multi-core designs on a single die, so power is becoming the bottleneck
- Complexity of adapting existing low-power methodology and tools—what we had before today was disjointed and incomplete flows from architecture all the way to GDSII.
cdnusers: How does the Low-Power Methodology Kit address these challenges?
Amjad: The Kit provides complete flows that are fully scripted and reconfigurable. It gives the designer an umbrella low-power flow that automates area, timing, and power exploration from concept, including design for manufacturing, using proven Cadence technologies and methodologies.
cdnusers: Now some personal questions. How do you concentrate when working? Any tricks?
Amjad: By looking at the big picture and keeping in mind the entire design flow that is in front of me as well as the system requirements. As an architect, you need to look at the entire system, not even just the chip. This helps me identify the gaps earlier while individual team members execute and deliver the flows. This helps me keep priorities in line.
cdnusers: Where do you do your best thinking?
Amjad: Early early morning, before early morning meetings start.
cdnusers: What do you do after a long day or week of working on low power problems to relieve your stress levels?
Amjad: Play with my 3 year old daughter. Just looking at her relieves a great deal of stress for me.
| 
About the author
Amjad Qureshi is a Technical Marketing Director and digital Kits architect in the Kits organization at Cadence. Mr. Qureshi has been with Cadence since early 2006 and has over 19 years of experience in chip design and verification. Prior to joining Cadence Mr. Qureshi was the Engineering Director at a multi-core DSP processor startup where he successfully managed 4 complex tape-outs. Mr. Qureshi held several management positions with IBM, Samsung and Phoenix Technologies. He has 14 US patents and has written several papers. Mr. Qureshi holds a Bachelor of Science and Masters of Computer Engineering from Case Western Reserve University.
|
| |
This content has been rated 3 out of 5 by other users |
|
|
|
|
|
|
|
|
|
|
| |
|
|
|