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 | |  | | | | | Virtuoso Multi-Mode Simulation 6.2 Improves Mixed-Signal Verification
An interview with Dr. Bruce W. McGaughy, Senior Architect
Cadence Design Systems | |
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At CDNLive! EMEA 2007 Cadence announced the release of Virtuoso Multi-Mode Simulation 6.2. cdnusers.org had the opportunity to discuss this release with Bruce McGaughy, Senior Architect for this new simulation technology.
cdnusers: What is your current involvement with Virtuoso Multi-Mode Simulation 6.2?
Bruce: As the platform architect, I oversee all aspects of product architecture, including how Multi-Mode Simulation interfaces with the Virtuoso platform and other Cadence products. I also take leadership of select new technology development projects, such as the development of the new DX fast digital simulation mode, in the Virtuoso UltraSim simulator. My responsibility is to architect the simulation products and their tight integration with Virtuoso to keep Cadence ahead of the technology curve in Custom IC design.
I also support Tiger Teams and, in some cases, lead Tiger Teams, which are teams that bring together field, marketing, product engineering, and R&D to work more closely with customers.
cdnusers: What are the challenges customers face with simulation today?
Bruce: We are finding that many customers are struggling with statistical modeling and simulation for 65nm designs, and the problems will only compound in 45nm technologies. Furthermore, the ever-increasing complexity of chips is leading to more verification challenges when all the parts are put together. This requires a comprehensive verification plan that can scale across digital, analog, RF and memory domains. At the same time, advanced processes require more verification for reliability, parasitics, signal integrity, etc. Virtuoso Multi-Mode Simulation has the breadth to span the various IC domains and the depth of technology to address the challenges of advanced processes.
cdnusers: What do you like most about this latest release?
Bruce: In the latest release, Virtuoso Multi-Mode Simulation 6.2, we also have a lot of great features, but I would highlight the major enhancements that have enabled it to deliver the most complete solution. Those include the verification flow and SpectreRF integration in AMS designer, the direct Spectre integration with Analog Design Environment, and the DX mode and EM/IR analysis flow in the UltraSim Simulator. These features greatly improve mixed-signal verification
cdnusers: How tightly is simulation integrated with the overall flow in this release?
Bruce: With every release we have introduced tighter integration within Multi-Mode Simulator and with the Virtuoso platform. The 6.2 release is particularly strong in delivering tighter integration. For example, we now have a seamless, direct integration with Analog Design Environment in the Virtuoso platform, resulting in significantly better runtime for DFY applications in particular.
cdnusers: Now some personal questions, Bruce. How do you concentrate when working? Any tricks?
Bruce: I find, if you enjoy your work and embrace the excitement of new technology development, concentration is the least of your concerns. You simply have to make each challenge fun and interesting. One trick I have found is drinking green tea throughout the day. It’s a habit I picked up several years ago when visiting Japan. It keeps you alert and helps to focus your mind, without the inevitable crash and burn effect of coffee!
cdnusers: Where do you do your best thinking?
Bruce: In my experience, collaboration with other architects or engineers often leads to breakthroughs. Any idea, no matter how original or good you think it is, becomes much better after brainstorming with others. I find there is nothing better than a white board, several colleagues, and a tough problem... and of course a cup of warm green tea. I also find technical conferences can stimulate new ideas, and again the hallway discussions with colleagues often yield the most interesting ideas. However, for me, the best thinking occurs on business trips to visit customers. There is nothing like the sobering reality of learning about your customer’s challenges in building the next great technology breakthrough, and how our products must improve to enable them to achieve their goals.
cdnusers: What do you do after a long day or week of working on Virtuoso to relieve stress?
Bruce:So many interests and so precious little time! It probably does not count as “stress relief”, perhaps more like a different flavor of stress, but I spend much of my free time with my 3 young daughters, Katarina (9), Natalie (7) and Isabel (2). We like to do outdoors and sports activities as a family, including hiking, windsurfing, skiing, etc. Personally, I play tennis regularly and keep in good shape by mountain biking and swimming. I love the challenge of playing new opponents on the court or getting to the top of Mission Peak a few seconds faster than the last time!
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About the author
Dr. McGaughy received a B.S. degree in Electrical Engineering from the University of Illinois at Urbana/Champaign and M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the University of California at Berkeley, in 1994, 1995 and 1997, respectively. He has conducted and published research in the fields of circuit simulation, device physics, reliability, electronic design automation, computer architecture, and fault tolerant computing. Prior to his current assignment, he worked for Integrated Device Technolgy (IDT), Siemens and Intel. In 1997, he joined Berkeley Technology Associates (BTA) which eventually became Celestry and was acquired by Cadence in 2003. He has led the architecture and development of the hierarchical FastSPICE simulator, the Virtuoso UltraSim Full-Chip Simulator, since its inception at BTA in 1999. More recently he led the circuit simulation R&D group at Cadence responsible for Spectre, Spectre RF and UltraSim products, from 2004-2005. Since that time, Dr. McGaughy has been the chief architect for Cadence simulation products.
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