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 | |  | | | | | Common Power Format - a Standard to Describe Power Architecture
Interview with Dr. Qi Wang, Engineering Director of the Synthesis Group
Cadence Design Systems, Inc. | |
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The community interviewed Dr. Qi Wang about his experience developing the Common Power Format recently donated by Cadence to Si2.
Q. Tell us about your background working with Low Power design software.
A. I have been working on low power design software for more than 11 years. During my PhD study, my research focus was on low power synthesis and power modeling for CMOS devices. After graduation, I joined Ambit Design Systems and architected and developed all the power optimization capabilities in BuildGates. After the acquisition of Get2chip, I became the architect to develop low power features in RTL-Compiler. Within 3 years, I brought RTL-Compiler from a tool with no power features to a tool with full range of low power support. RTL-Compiler low power synthesis has a 100% benchmark win rate so far and becomes a key differentiator of Cadence low power technology compared with competitors. Since 2005, I have been deeply involved in the Power Forward Initiative and a key architect of the Common Power Format.
Q. What is the one new thing for engineers designing for Low Power should know about the new Cadence Low Power flow?
A. Power Forward Initiative is Cadence’s vision for future low power designs. It spreads out in all aspects of the design flow. With strong technologies in design, implementation and verification, and the leadership of driving the Common Power Format to integrate all these features in the design flow, Cadence has positioned itself as the undisputable industry leader in low power designs.
Q. Can you tell a little bit more about the Common Power Format (CPF)?
A. Verilog is the standard to describe functionality and SDC is the standard to describe timing. There has been no standard to describe power architecture. With the increasing popularity of advanced low power techniques such as power shut-off and dynamic voltage frequency scaling which effectively change the original functionality of a design, it is becoming apparent that a power standard is needed to describe such power design intend at early design cycle and understood by implementation and verification tools in the whole design flow. Common Power Format was developed by a group of key Cadence architects from different Business Units to meet such requirement. Recently Cadence donated the format to Si2 which will drive the standardization of the format.
Q. Will the opening of CPF give any advantages to our competitors?
A. In the history of EDA, there has never been an example where business can be built upon a file format. The business is always centered on tools and flows. To develop successful tools and flows based on CPF, it is cruicial to collect customer feedback early on. That is the precise reason that we formed the Advisory Board of PFI in May this year. However, this made it unavoidable that our competitors may know about the effort and develop a copy-cat format to slow down the momentum of CPF and confuse the market about the leadership of Cadence in low power designs. As a result we have been focusing on developing tools and flows based on CPF from the birth of the format. The first wave of product announcements will be in January 2007 from key products in the Incisive and Encounter platforms. More product announcements will come in for the rest of year and plans to have the format supported by other platforms are either in place or under development. In summary, as a company, there is a clear strategy in place to deploy the CPF based products and flows to capture the full value of CPF. With that in mind, opening CPF is not a concern at all but a right step of the overall strategy to achieve our business goals.
Q. Now some personal questions. How do you concentrate when working? Any tricks?
A. With so many things going on everyday, I never have problems to concentrate on working. However, the biggest challenge to me is to know what the right things are to focus on. I believe the key is to understand the big picture and know what the long term objectives are. With the long term goal set, I like to evaluate the changing situation from time to time and adjust my schedule and plan to make sure that I focus on the right things all the time.
Q. Where do you do your best thinking?
A. Where ever I have no access of emails!
Q. What do you do after a long day or week of working on Low Power problems to relieve your stress levels?
A. Both of my daughters are taking piano lessons. Sitting with them while they practice pianos everyday makes me feel relaxed. Jogging and yoga are also good ways to relieve the stress.
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Dr. Qi Wang discusses the Common Power Format recently donated by Cadence to Si2 and the Cadence Low Power flow.
About the author
Dr. Wang is an Engineering Director of the Synthesis group at Cadence Design Systems. He is the architect of the low power synthesis technology in RTL-Compiler and involved in many low power related projects from other business units in Cadence. Currently he is also responsible for defining Common Power Format and driving R&D activities in the Power Forward Initiative. Before working on RTL-Compiler, Dr. Wang was a key architect of the Low Power Synthesis in BuildGates synthesis tool. His research interests include low power synthesis, high level synthesis and timing optimization. He has more than 20 papers published in various international conferences and journals. He also holds various US patents on synthesis and low power technologies.
Dr. Wang holds a B.S. degree in Applied Electronics from Shanghai Jiao Tong University, an MSEE degree from Southern Illinois University and a Ph.D degree in Electrical and Computer Engineering from University of Arizona. |
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