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 | |  | | | | | Epoch Microelectronics Explores Cadence RF Design Methodology Kit for Wireless Applications
Aleksander Dec, Vice President and Co-Founder
Epoch Microelectronics, Inc. | |
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cdnusers interviewed Aleksander Dec, vice president and co-founder of Epoch Microelectronics, Inc. Dr. Dec has 11 years experience in analog and RF IC design including GSM and WCDMA cell phone; satellite and cable TV; WLAN and audio applications. Dr. Dec, who holds multiple patents, has authored and co-authored numerous conference and journal publications.
cdnusers: Alex, can you tell us something about Epoch Microelectronics?
Aleksander: We are a 10-person design house company. We specialize in analog, RF, and mixed-signal ICs for the cellular phone, satellite, cable markets. Today, because of the market, our designs are almost 100 percent RF and wireless. The company has extensive experience in the design of various parts and components for transceiver ICs such as integrated VCOs, high frequency dividers, and complete RF front-end circuits for the quad-band GSM/DCS cellular phone standard.
cdnusers: What RFIC technologies do you concentrate on?
Aleksander: WLAN, 3G, Zigbee, GSM and WCDMA.
cdnusers: What challenges are you seeing?
Aleksander: Shorter design cycles, bigger chips, putting the whole transceiver into an SoC, integrating different standards into one radio. There is also financial risk.
cdnusers: Everyone is talking about shorter cycles, can you pin that down for us?
Aleksander: Cell phones are a consumer product. People want new features every year, more functionality. To do a highly functional chip in that time frame is very hard. Now, we have design teams working on 2007, 2008, 2009. Many schedules are extremely aggressive—we have had to do layout in a month, the entire design in three to six months.
cdnusers: How do your customers benefit from the designs you work on?
Aleksander: We work on the same clock as our clients, starting layout at the same time, and letting our customers’ design teams focus on the digital piece of the design, while we focus on the RF—getting RF right the first time is challenging; it’s our specialty.
cdnusers: What are some industry trends that are driving your design requirements?
Aleksander: Multi-standard radio transceivers on one chip—GSM and WCDMA. People want a cell phone to work wherever they are in the world.
cdnusers: Do you currently have an optimized RF Design flow?
Aleksander: As a design house, we adopt to our customer’s design flows. Generally, we use the Cadence flow—except for synthesis where we use Synopsys.
cdnusers: What caused you to first look to the Cadence RF Design Methodology Kit as a possible solution to RF design and analysis problems?
Aleksander: Honest answer: we didn’t know about it until Steve Gendron (Cadence Account Executive) came in and asked us to have a look at it. Once we did, we became interested.
cdnusers: What has been your experience with the Kit so far?
Aleksander: The most valuable part of the kit was the five days of applicability training we received from Alan Whittaker (Cadence engineer). We learned about features in Cadence tools that we hadn’t had time to look at—you see the button on a new release but you are busy and you don’t have time to find out about it. It was great to learn we already had a number of things in the tools that resonated with problems we were having.
cdnusers: What features? Can you give us an example?
Aleksander: For one, stability (STB) analysis. We have been a Cadence user for many years and weren’t aware of this feature. During training, Alan ran us through some opamps and did stability analysis on them. The results were such that, now, we pretty much always use the STB function for opamp design.
cdnusers: Anything else?
Aleksander: Yes, learning to use VPCM (Virtuoso Passive Component Modeler) for inductor simulation and synthesis has been valuable. After learning about it, we changed our process and are now using it for most of our tape-outs.
cdnusers: What is the value of VPCM to your process?
Aleksander: Accuracy. For example, after tape-out on a VCO (voltage controlled oscillator) operating in the 1.2 GHz range, we found we were off by 10 to 20 percent—we missed the target. By adopting the VPCM and Assura RF flows and managing parasitics by simulating the chip with extracted views, we got that percent down to 0.9 to 1.6 percent.
cdnusers: Anything else about the Kit that you have found beneficial?
Aleksander: Using envelope analysis for verification. We had a crystal oscillator design which had measurement problems. When we went through it and set up the Cadence envelope analysis, we could see the problems during simulation that we were seeing in the measurements—the technique predicted the problem.
cdnusers: What about PLL (phase lock loop) simulation? The kit offers some new technology in that area.
Aleksander: One of the challenges of PLL design is how to get the Sigma Delta converter simulation done quickly. We haven’t solved it yet, but we are looking forward to exploring this further. Until now, we have been using MATLAB/Simulink in our design flow, but we are thinking Verilog A may be a better way to go. We think it may be easier to debug.
Cdnusers: What do you use the kit for now?
Aleksander: For reference, for the documentation and for training new engineers.
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About the author
Aleksander Dec is the Vice President and Co-Founder of Epoch Microelectronics, Inc. Prior to founding Epoch, Dr. Dec conducted research at Columbia University on Microwave CMOS VCOs utilizing RF-MEMS devices. In addition, Aleksander Dec worked at Silicon Circuit Research Department of Lucent Technologies, Inc. on mixed-signal and RF IC design for GSM transceivers.
Dr. Dec has 11 years of experience in analog and RF IC design, including GSM & WCDMA cellphone, Satellite & Cable TV, WLAN, and audio applications. Dr. Dec has authored or co-authored 16 conference and journal publications, and holds multiple patents.
Aleksander Dec is a member of the Institute of Electrical and Electronics Engineering (IEEE) and holds B.S. (’93), M.S. (‘95), and Ph.D. (’98) degrees in Electrical Engineering from Columbia University.
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