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 | |  | | | | | Virtuoso platform IC 6.1 Product Launch
Interview with Product Engineer Akshat Shah
Cadence Design Systems, Inc. | |
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Q. Cadence just launched Virtuoso platform IC 6.1. As a Product Engineer on this platform, tell us about your background working with this technology.
A. Well, I have mostly been involved with the simulation environment side in IC 6.1, specifically the ADE XL and ADE GXL technologies. I have been involved with numerous other fellow Product Engineers in everything – from defining product requirements, talking to early customers, training early customers, training support staff, receiving feedback and incorporarting it into the product and validating the functionality before the product is released. As a product engineer you are intimately involved with every aspect of product design and you are the central liaison point between marketing, R&D, customers, sales, PV etc. It has been really exciting to watch this new platform evolve over the last few months. This new platform is a massive accomplishment by the entire Virtuoso platform team and I think customers are going to be delighted to see the true front to back integration that IC 6.1 brings to the table for the design challenges of today’s modern technologies.
Q. In any new release there are a lot of new features that benefit users, but in your opionion, what is the one most important new feature to users of this product?
A. Well for the IC 6.1 platform, the biggest and most important feature is the integrated front to back flow with constraints as the back-bone. No doubt about it! And this integration will just get tighter and tighter with each release. But I am sure the platform architects got that one covered!
From an environment standpoint, the biggest feature is the new simulation environment! We have combined the best of the IC 5.1.41 ADE environment, the VsdE environment and the NeoCircuit environment into a unified environment. Integration is of course a de-facto advantage – but on top of it, Cadence now provides a true multi-test multi-corner simulation environment that is truly integrated into your design flow! I could throw out advantages like designer productivity, shortened design cycle times etc. etc., but anyone reading this who does custom mixed-signal design will immediately realize the advantage by simply reading a "true multi-test multi corner simulation environment".
Q. Tell us how this feature works
A. In IC 5.1.41 environment users were generally limited to running one simulation across one corner with the ADE environment. Now, imagine setting up multiple simulations in multiple ADE windows and running them simultaneously and seeing all the results in one central place. Well – that is what the new simulation environment gives you! Setup multiple simulations – one at a time. Setup multiple corner cases to run your simulations across. And run them simultaneously – not one at a time. Run them all simultaneously and view the results in one central place and compare your results. All the results are stored in one central place. It’s that simple. If you are an ADE user, you should be able to pick up this environment because we have built it on top of what you already know – ADE. If you are not an ADE user, this environment should convince you to switch over!
Q. Now tell us about a couple more features that users will find helpful in creating their designs.
A. Well – I think the one feature that has been well received and applauded across the board is the new parasitics flow in IC 6.1. Estimate your parasitics during simulation before you hand off to layout. Eliminate the costly iterations between your circuit designer and your layout engineer! Stop over-designing and get the most performance out of your circuits. Run Monte Carlo analysis with your parsitics estimates and make sure you produce robust designs. Couple this with the multi-test environment and you have a compelling design flow in IC 6.1. Digital started accounting for timing effects early in the design cycle 15 years ago – it’s time for mixed-signal design to follow that path with parasitic estimation!
The second feature that will be well received is optimization. Historically, optimization has not been well received in the mixed-signal community. But now with proven optimization technologies that have been on the market for years, the community is beginning to warm to this concept. In today’s day and age, with the powerful computing resources available, why should your designers worry about the mundane task of running simulation after simulation to get the most performance out of your circuit. And at 65nm and below, the design challenges are getting more and more complex. Let your designers guide an optimization engine that automatically and efficiently runs your simulations and optimizes your power and area and let your designers concentrate on the tasks that truly matter in a design cycle – getting a robust design out the door and meet your time to market constraints.
Q. Now some personal questions, Akshat, how do you concentrate when working? Any tricks?
For me, it is music. Period. If I need to concentrate on something, there is nothing better than putting on my headphones and blasting music and tune out everything around me. Most hearing experts won’t recommend the “blasting” part, but I figure doing it for short periods shouldn’t do much long term damage
Q. Where do you do your best thinking?
As strange as it sounds, at home lying on my couch. Just have some sporting event on in the background – I prefer ice hockey or baseball – the background chatter seems to generally help the thinking process.
Q. What do you do after a long day or week of working on Virtuoso to relieve stress?
Running – it is one of my most favorite activities in the world. Those who think that runner’s high is a myth has never really tried running on a regular basis. I love the feeling after running for 30-40 minutes – it completely refreshes your mind. For a few minutes nothing else matters but the running...
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An Interview with Virtuoso Platform IC 6.1. Product Engineer Akshat Shah.
About the author
Akshat Shah is currently working at Cadence Design Systems as a product engineer for ADE XL and ADE GXL. He has been working on the IC 6.1.0 platform since January 2006. Prior to this, he was Product Engineer for the NeoCircuit DFM technology since 2003. Before joining Cadence, he was an Applications Engineer with Neolinear, Inc. and supporting the NeoCircuit and NeoCell technologies since 1999. Akshat obtained his BSEE from Carnegie Mellon University in Pittsburgh in 1999. |
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