 | With its patnet-pending concurrent S.M.A.R.T. routing (unified Signal integrity, Manufacturing Aware, Routability, and Timing optimization) and superthreading technologies, NanoRoute Ultra takes an already placed gate-level netlist and generates a tapeout-ready GDSII design database that meets the timing, signal-integrity, process-rule, and manufacturability requirements of nanometer-scale design.
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Sarah Lamont, Silicon & Software Systems (S3)
An Encounter NanoRoute Ultra user for 2.5 years Sarah Lamont has developed large SoC's at top and block level, IP hardening and non-hierarchical designs down to 65nm technology for high speed and computing markets using Encounter NanoRoute Ultra. | |
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