|  |  | Encounter RTL Compiler
Delivering global synthesis for timing closure, Encounter RTL Compiler works with existing design flows to increase chip performance, decrease die size, and reduce power consumption. The global-focused mapping algorithm examines the entire design space to produce the logic structure for implementation.
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|  | | Encounter Conformal
A formal verification technology used for equivalence checking, design-constraint management, and low-power design verification, Encounter Conformal provides complete verification solution and allows users to find bugs in the design and constraints earlier in the design cycle using a comprehensive debug and analysis environment.
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|  | | SoC Encounter
SoC Encounter is an integrated netlist-to-GDSII or RTL-to-GDSII configuration for flat, hierarchical or advanced designs of up 100M gates. Various configurations may include First Encounter, RTL Compiler, NanoRoute, supporting floorplanning, placement, power planning, power routing, clock tree synthesis (CTS) signal routing and extraction.
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|  | | First Encounter
First Encounter generates the physical performance characteristics for your design, a silicon virtual prototype. It includes built-in floor planning, Amoeba placement, trial routing, extraction, and clock tree synthesis engines. First Encounter uses a common timing infrastructure for estimating static timing performance.
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|  | | Encounter NanoRoute Ultra
With its patnet-pending concurrent S.M.A.R.T. routing (unified Signal integrity, Manufacturing Aware, Routability, and Timing optimization) and superthreading technologies, NanoRoute Ultra takes an already placed gate-level netlist and generates a tapeout-ready GDSII design database that meets the timing, signal-integrity, process-rule, and manufacturability requirements of nanometer-scale design.
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|  | | CeltIC
CeltIC Nanometer Delay Calculator (NDC) is an SI-aware delay calculator providing you with a unified timing solution that accurately accounts for the impact of crosstalk and IR drop on both delay and functionality, calculating delays to within 3% of SPICE. CeltIC NDC detects functional errors due to double clocking and bootstrap noise as well as offering on-the-fly critical path simulation for easy validation of SI-induced waveform effects. CeltIC NDC reduces false SI failures via glitch propagation and analyzes flat multi-million-gate designs in a few hours or less.
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|  | | Encounter Test
Encounter Test is used in nanometer designs to test for functional device failures and to ensure design specifications are met. Encounter Test Architect adds function to the design to enable better manufacturing test. Encounter True-time Test generates test patterns used in manufacturing test. Encounter Diagnostics help identify the root cause defect of a manufacturing test failure.
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