 | The Incisive Formal Verifier allows the designer to begin verification while designing RTL blocks, before testbench development and simulation. It also contains a set of formal engines, automating the engine selection process by selecting optimal engines for each run. Incisive Formal Verifier provides extensive design language support, including Verilog, SystemVerilog, VHDL and mixed-language and also supports assertions written in Property Specification Language (PSL), SystemVerilog Assertions (SVA), Open Verification Library (OVL) and the open source Incisive Assertion Librarary (IAL).
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Raimund Soenning, Micronas GmbH
Raimund Soenning is currently with Micronas GmbH in Munich, Germany working as verification engineer with large SoC designs for digital TV applications. | |
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