 | The Incisive Unified Simulator natively supports Verilog, SystemVerilog, VHDL, SystemC, SystemC Verification Library, PSL, SVA and OVL. The Incisive Unified Simulator increases RTL performance with native transaction-level simulation and optional Acceleration–on-Demand. It also reduced testbench development up to 50% with transaction-level support, unified test generation, and verification component re-use.
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