|  |  | Incisive Palladium Series
Palladium is an accelerator and emulator providing a flexible debug and advanced verification environment that includes transaction and assertion-based acceleration solutions. The Palladium systems support multiple concurrent users and remote access, enabling concurrent verification debugging of hardware and embedded software before silicon is available.
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|  | | Incisive Specman Series
Specman uses e verification language to capture rules from executable specifications, using the information to automate verification and support design re-use. Specman Elite's constraint-driven test generation allows designers to specify constraints to create tests in the functional test plan or on-the-fly, making it possible to detect even hard-to-reach corner cases.
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|  | | Incisive Xtreme Series
The Xtreme series of hardware-assisted verification systems provide simulation, acceleration, and emulation that automates the verification process. The Incisive Xtreme systems have a compiler that automatically maps sections to emulate with the RCC engine and builds a native-compiled simulation image for sections that remain in the software simulator. A patented hierarchy-extracted mapping technique automatically maps designs onto reconfigurable processors, and the event-drive RCC algorithm optimizes usage and provides high-performance simulation.
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|  | | Incisive Unified Simulator
The Incisive Unified Simulator natively supports Verilog, SystemVerilog, VHDL, SystemC, SystemC Verification Library, PSL, SVA and OVL. The Incisive Universal Simulator increases RTL performance with native transaction-level simulation and optional Acceleration–on-Demand. It also reduced testbench development up to 50% with transaction-level support, unified test generation, and verification component re-use.
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|  | | Incisive Formal Verifier
The Incisive Formal Verifier allows the designer to begin verification while designing RTL blocks, before testbench development and simulation. It also contains a set of formal engines, automating the engine selection process by selecting optimal engines for each run. Incisive Formal Verifier provides extensive design language support, including Verilog, SystemVerilog, VHDL and mixed-language and also supports assertions written in Property Specification Language (PSL), SystemVerilog Assertions (SVA), Open Verification Library (OVL) and the open source Incisive Assertion Librarary (IAL).
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|  | | Incisive Enterprise Manager
Incisive Enterprise Manager automates the verification process from plan to closure for chip and systems projects. RTL Design Teams developing blocks and chips may use the related Incisive Design Team Manager. They both analyze and report metrics that measure and drive the verification process from an executable plan.
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