 | | | | This week from CDNLive! Silicon Valley | | | | | |  | | Featured podcasts, commentary from attendees, and special articles highlighting all the exciting things that happened at the conference.
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 | | Podcast - Mike Fister interview on new technology announcements
Mike Fister talks about CDNLive!, and kicked off the conference by unveiling Virtuoso 6.1, the new custom chip design platform, and Xtreme III, a hardware-assisted verification system.
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 | | Podcast - Collaborative Innovation Powers Sony PS3
The cell chip is the heart, soul and brain of the Sony Playstation 3 game console. Cell is essentially a super-computer on a chip, and when PS3 comes out this fall, it’s going to take gaming to a whole new level. Mike Fister, President and CEO of Cadence Design Systems, and Jim Kahle, IBM Fellow with IBM Corporation and Director of Technology for the Austin-based Center for Cell Technology, talked with PodTech.net about the collaborative innovation that went into development of Cell.
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 | | Podcast - Customer is Key in Designing the Future
Ted Vucurevich, Cadence CTO and Cadence Designer Network steering committee member, talks about the future of the chip design process and the customer's changing role in driving design systems, processes and solutions.
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 | | Podcast - CDNLive! Keynote: Unlocking Creativity in Electronics Design
Mike Fister's keynote address to kick off CDNLive!. "How do we help unlock that creative element and allow all of us as humans to continue to move up and expand the creative element, and not the mundane? That's what automation exists for, and that's my passion for being in the electronics industry, and that’s why we exist at Cadence."
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 | | Podcast - CDNLive! Keynote: Collaborative Innovation – Designing in the Broadband Era
Jim Kahle, IBM Fellow with IBM Corporation, revealed some of the secret ingredients of innovating through collaboration during his keynote address at CDNLive Silicon Valley. Kahle was a key player in the creation of Cell Broadband Engine processor, an accelerator extension to IBM Power Architecture chips, that will run the next generation Sony Playstation, the PS3, due out this fall. This podcast brings you excerpts from his keynote address.
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 | | September 14, 2006 - 12:00pm
Ross Weber on CDNLive! technical presentation applicability
For 2 years now I've come to CDNLive and have been inspired by the technical presentations. It seems like from each one of them, I am able to take a little bit back to the office. From affirming something that we are already doing to seeing a new way to do something that we are already doing to seeing something completely new that we should be doing. Also, interacting with my fellow users and the Cadence gurus has been extremely helpful with my more detailed questions. I hope next year to get even more people from my company to this great even!
Ross Weber, Senior Hardware Engineer, Unisys, Formal Analysis Forum Moderator |
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 | | September 13, 2006 - 7:00pm
Insights received from CDNLive presentations
The most interesting talks here at CDNlive! are the presentations by users for users. For instance I liked the one about "the use of Virtuoso Layout Manager for DFM Optimization." The presenter discussed the usability of the tool in an informal easy-to- understand way. When I hear from users that they have successfully used the tool, that makes me interested in looking at that tool also. Another presentation I found interesting was "Using C++ for modeling." The presenter told us "innovation is done by people who understand the circuits". To understand the circuits you have to analyze properly and that is where the behavioral model comes in. Another good presentation was about RF Simulation techniques. The Cadence presenter explained to me in 45 minutes what I have been wondering about for two years.
Herman Janssen, AMS Design Flow Architect, NXP, Custom IC Forum Moderator |
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 | | September 13, 2006 - 5:00pm
Observations on SPB content
You who did not attend CDNlive! this year really missed a great series of presentations this year – the amount of information is better than last year and I am sure will be even better next year.
I work with schematic capture tools and this year there are two parallel SPB tracks, one for board layout and one for schematics, so there have been more papers related to the schematic capture tools and area of interest.
Harry Bartley, Applications Engineer, Tektronix |
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 | | September 13, 2006 - 5:00pm
Remarks from a returning CDNLive attendee
This event is much better than last year. Organization is much better, bigger place, sessions are spaced out well – more breaks to network with other users. Sessions were very good – technical panels were excellent – I had questions and received good answers that I was looking for. Everyone had a chance to ask questions and had time afterwards to talk with the experts. I enjoyed the luncheon comedian, he was a former chip designer turned comedian.
Sufai Salim, CAD Engineer, Analog Devices |
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 | | September 13, 2006 - 4:30pm
CDNLive SiP Panelist Comments
I was a panelist in the SiP technical session moderated by Senior Editor Mike Santarini of EDN. One of the things I found interesting about the panel was that each of the panelists described how important communication is in completing a successful SiP implementation.
In true Sip form, the session, instead of presentation followed by QA to the panelists, was a true interactive session with audience and panelists interacting in a free flowing manner.
The QA session represented the requirement for two way interaction in the SiP design space. The panelists were asking questions of the audience as well as the audience asking questions of the panelists. This is the type of collaboration necessary for SiP success.
Steve Lowder, VP of Design, Amkor |
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 | | September 13, 2006 - 3:30pm
CDNLive Review by Randy Bye
This year's event looks to be another success. I've seen some excellent user papers and have had the opportunity to talk one-on-one with Cadence R&D. It has also been great to be able to discuss tool issues with other users to learn how they are dealing with similar issues. The CDNLive conference has once again provided an outstanding forum for learning the latest and greatest information about existing and future PCB tools.
Randy Bye, Sr. Hardware Engineer, Unisys Corporation, PCB Forum Moderator |
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 | | September 13, 2006 - 2:30pm
CDNLive Event Impressions from Amit Chandra
The CDNLive! event is well organized and informative from different technology perspectives. The roadmaps are particularly good - they give more insight into the longer term on the products, more than just the next few months. Looking forward to tonight's event, where we actually get to see products demonstrated first hand - where the rubber meets the road.
Amit Chandra, P.A. Semi |
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 | | September 13, 2006 - 12:00pm
CDNLive Highlights from Joe Covey
Mike Fister did well yesterday with his keynote. Steve Glaser's presentation was very interesting to us since he mentioned the Cadence Formal Verification Kit with ARM. I also particularly enjoyed Eric Filseth's Torino presentation which talked about the collaboration with Cadence on our synthesizable cortex-8 core to make the core more easily synthesizable.
Joe Covey, EDA Relations Manager, ARM |
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 | | September 13, 2006 - 11:00am
Review of Cadence Conformal LEC Presentation
If you missed Erik Seligman's presentation on "Best known methods for using Cadence Conformal LEC at Intel", you'll want to look forward to the posting of his presentation slides on the CDNusers.org website.
Eric gave some great practical methods for dealing with some of the most frustrating and vexing issues that we encounter everyday when using Conformal LEC: abort points and non-equivalent points, as well as advice for auditing for false positives.
Erik suggested a number of techniques to get past abort points, including, where appropriate, using the commands/options:
> set compare effort complete
> analyze datapath -merge [-effort high]
> compare -parallel <machine_file>
To see more of his methods and suggestions, take a look at his presentation when its available.
This morning (Wed), I'm looking forward to seeing Lam Ho of TI present his paper on
"Formal and Structural Analysis of Power Management Designs Using Conformal Low Power",
If you have impressions, feedback, comments about any of the papers that you've seen, please feel free to post them to the cdnusers.org forum
Dave Goldberg, Digital IC Forum Moderator, Synfora |
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 | | September 13, 2006 - 10:30pm
Overall Impression of CDNLive
Pretty good conference – got enough information here. Food is great, presentations were good, but some were too short.
Tao Ding, CAD Engineer, Conexant |
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 | | September 13, 2006 - 9:00am
Overall Impression of CDNLive
This years CDNLive event is everything I expected it to be. I found great value in being able to network with fellow Cadence Users and the Cadence staff. Of great interest to me were the numerous technical papers presented by other Cadence users. I found the PTF Manager paper presented by Chris Day of Motorola to be of particular interest to me. It gave me insight into how our Company might choose to implement a similar functionality to improve our design process. CDNLive is an excellent venue to improve your knowledge of Cadence products and meet other individulas that share the same passions.
Charlie Davies, Harris Corporation, PCB Forum Moderator |
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 | | September 12, 2006 - 11:00pm
CDNLive! First Day wrap-up from Eric Venditti
This is my second year at CDNLive and I have to say that I am pretty excited about this year's conference. As a steering committee member this is the realization of a year of work and so far I am amazed at the improvement over last year. The new facilities are a lot nicer and more functional than the one from last year. The room and infrastructure are also amazing.
I would also like to say I really enjoyed all the presentations I attended and I would like to thank everybody for submitting so many quality papers. The selection was harsh and so harsh that we negotiatied with other tracks to get some of their slots. This introduced a bit of confusion on the schedule but I hope people will forgive us and enjoy the presentations.
In the other hand, I have to say I am disappointed in the cdnuser digital IC community. From attending the papers I know we have plenty of attendees, however the 2 tables at the Tuesday luncheon were almost empty. I was looking forward to the opportunity to meet a few of you and get feedback on what we can do to get some more dynamic forums and more participation but it didn't happen.
But I am pretty excited to see people show an interest in a new data management forum and being able to identify a volunteer to monitor this forum right away. I hope this will happen as this is one of the most challenging problems we are facing today across disciplines and I am looking forward to see the community share its experience and hopefully inspire the industry to attack and solve this problem.
To conclude I would like to thank all of you for attending and for making this event, YOUR EVENT, a success.
Thanks,
Eric Venditti, Design Engineer, Texas Instruments, Digital IC Forum Moderator: Synthesis and Test |
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 | | September 12, 2006 - 7:00pm
Interview with Virtuoso Platform Product Engineer Akshat Shah
Find out about the new Virtuoso Platform IC 6.1 from Product Engineer Akshat Shah.
more » |
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 | | September 12, 2006 - 4:42pm
Comments on Xtreme III benchmarking
At SUN the class of processors we build requires constantly bigger capacity and higher throughput to enhance our Verification productivity. We were excited when Cadence gave us the opportunity to benchmark the next generation of Xtreme hardware. Using our open SPARC design as a benchmark we found it doubled the capacity and performance. Having collaborated with the Extreme team from the inception, I was happy to be a part of today's announcement of Xtreme III.
Jai Kumar, SUN Microsystems |
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 | | September 12, 2006 - 12:30pm
Comments on Jim Kahle keynote
The presentation by Jim Kahle, IBM Fellow, this morning had a lot of good, useful information, both technical and general. The Processor architecture visualization was impressive. The video demonstrated how the processor took the information from a satellite, processed it internally, then output the information as a 3D map. Hopefully this demo will be available on the website.
Li-Siang Lee, Forum Moderator, Digital IC |
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 | | September 12, 2006 - 11:00am
Interview with Xtreme III architect Ping–Sheng Tseng
An inventor and the system architect of the Xtreme system discusses the latest release.
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 | | September 12, 2006 - 8:00am
Welcome to CDNLive! SV 2006
Here we are at the second annual CDNlive! at Silicon Valley. It is a very exciting time for us – the steering committee went out of their way to develop a content rich program here in Silicon Valley and I believe we have accomplished that task. We received over 200 abstracts to build 7 parallel tracks for a three day event. We made improvements based on feedback from those attending last year - we had more time to plan and it shows in the program. One of those improvements was moving to the San Jose Convention Center to accommodate increased attendance. This is a great opportunity to network with users that do the same job you do.
Mike Catrambone, Chairman, Cadence Designer Network |
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 | | September 11, 2006
Interview with Cadence IC6.1 architect, Don O'Riordan
Don O'Riordan discusses what he believes is the one most important feature of the new Virtuoso release.
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