Digital IC Zone


		Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure March 5, 2008, Narayanan Thondugulam - P.A. Semi Describes the use of Cadence Chip Optimizer for design closure in conjunction with SoC Encounter GXL-based place-and-route flowsRead more »

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Routing Based Yield Optimization Preserving Timing

November 6, 2007, Pierre-Olivier Ribet - Cadence Design Sysems

Presented at the SAME conference in Sophia Antipolis, France, this methodology is able to apply different kind of optimizations according to the criticality of nets.Read more »

The Art and Science of Pin Placement for Hierarchical Floorplanning

September 27, 2007, Jack Benzel - Avago Technologies

Winner of the People's Choice Award in Digital Implementation at CDNLive! Silicon Valley 2007 presents advanced topics in pin placement.Read more »

Interview: Making Reliable Models for SSTA

September 10, 2007, Prashant Maniar - Stratosphere Solutions, Inc.

Prashant Manier believes the current methodology of process characterization at 45 nm is not a good predictor of performance in the presence of variability. This interview explores lower node design methodology.Read more »

Interview: Freescale's Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges

August 3, 2007, Alex Albuerne - Freescale Semiconductor

Alex Albuerne, Freescale Semiconductor, discusses Encounter Timing System in Freescale's sign-off process. Read more »

Interview: Logic Designers Get Physical

July 9, 2007, Matt Rardon - Cadence Design Systems

Matt Rardon discusses physical predictability and how the Cadence Logic Design Team Solution closes the gap between logical and physical views of a design.Read more »

Improving Productivity Using Formal Analysis by Designers

June 15, 2007, Eric Faehn - STMicroelectronics

This Best Paper Award in the Digital area at CDnLive EMEA discusses several important aspects of deploying formal analysis in recent projects at STMicroelectronicsRead more »

Interview: Logic designers expand horizons

June 4,2007, Nimish Modi - Cadence Design Systems

Interview describing the Cadence Logic Design Team Solution—a cross-divisional effort that covers all of the technologies from the Encounter and Incisive platforms relevant to logic designRead more »

Handling Design Variability through Encounter SSTA

April 30, 2007, Parveen Khurana - Cadence Design Systems

Describes the rationale behind using SSTA, SSTA modeling requirements and Cadence's SSTA solution (Encounter SSTA).Read more »

Fast and Accurate Statistical Cell Characterization with Spectre

April 18, 2007, Ken Tseng - altos Design Automation

Accurate statistical timing analysis needs accurate statistical cell models, which in turn requires a new approach to cell library characterizationRead more »

Encounter 6.2: Reduce Duplication and Minimize Power Domain

April 4, 2007, Mui-Chwee Tong - Cadence Design Systems

>The release of Encounter 6.2 brings both feature maturation and new features to digital IC designers. Mui-Chwee Tong briefly discusses the most important features.Read more »

Experiencing Encounter Solutions for Low Cost Products

February 28, 2007, Davide Casalotto - ST Microelectronics

Unfortunately CAD vendors are usually more interested to address the new complex issues ...than to focus on low end low cost products.Read more »

Implementation of the SoCDE flow in FMS - the Flow Developer's Perspective

February 12, 2007, Dimitar Kavalov - NXP

Discusses the development effort for converting the current release of the SoCDE flow into an easy to use...Read more »

An Innovative Flow to Implement Large Scale Design Changes in the Final Stages of Physical Implementation

February 5, 2007, Amit Bandlish - University of Southern California

The technique presented aims at minimizing the design cycle time for implementing critical-path ECOs Read more »

A Different Approach to Structured ASIC

January 29, 2007, Michael Sydow - Lightspeed

Design teams are confronted with increased deep sub-micron technology challenges, while they also must be sensitive to the cost and risk of development of the product.Read more »

Cadence Conformal LEC – the Intel Experience

January 15, 2007, Itai Yarom - Intel

This presentation explores how to use the Cadence Conformal LEC tool capabilities to verify different types of designs. In particular, it focuses on the Conformal Ultra capability for verifying complex data-path synthesis and layout. We will use it together with the set effort "complete" command, in order to force the Cadence Conformal LEC to compare all the aborted state points. The design we present is a 1 Gigabit Ethernet chip with around 10 million standard cells.Read more »

Encounter SmartKit: The Digital On Top Implementation Platform for STMicroelectonics SmartPower Applications

January 9, 2007, Lyes Djama - STMicroelectronics

SmartPower, also known as "BCD", in one of the main process families used at STMicroelectronics. Its main feature is the integration in the same chip of CMOS, Bipolar and Power DMOS devices, supporting up to 90V. Due to the special nature of the process, a Digital Implementation Flow for SmartPower designs requires special attention to specific needs like irregular Block Shapes for Digital IPs to be assembled at the top-level, with very challenging block pin management...Read more »

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