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Functional Verification Zone


Interview: Verification Planning and Management Methodology Focuses on All the Right Things

March 24, 2008, Ze'ev Shtadler - Cadence Design Systems

Verification Planning and Management is rapidly becoming accepted as an important technical discipline for advanced designs.Read more »


Interview: Coverage-driven Random Verification

February 7, 2008, Apurva Kalia - Cadence Design Systems

Coverage-driven random verification methods are supported in the Cadence® Incisive 6.2 software release. Apurva discusses how to take advantage of this solution .Read more »
Interview: By Popular Demand—SystemVerilog Open Verification Methodology

January 10, 2008, Tom Anderson - Cadence Design Systems

Cadence and Mentor Graphics announce the Open Verification Methodology for SystemVerilog available for download. This interview discusses the relevance of the announcement. .Read more »
Interview: Closing in on Profitability with Leading-Edge Verification Practices

December 5, 2007, Erik Panu - Cadence Design Systems

cdnusers talked to Cadence Engineering Group Directors Mike Stellfox and Erik Panu to find out when and how to deploy the Incisive® Plan-to-Closure Methodology. .Read more »
Verification of Low-Power Designs using CPF

October 23, 2007, Noah Bamford - Freescale Semiconductor

CDNLive! 2007 People's Choice Award presentation, illustrates techniques that maximize vertical reuse.Read more »
Simplifying Vertical Reuse with Specman Elite

October 5, 2007, Mark Strickland - Cisco Systems

CDNLive! 2007 People's Choice Award presentation, illustrates the advantages of using a CPF-based flow over an ad-hoc solution.Read more »
Translation of an Existing VMM Testbench into URM

September 27, 2007, Kelly D. Larson - Analog Devices

MVP presentation at CDNLive! 2007, highlights which aspects of the translation were straightforward and which aspects required more attention.Read more »
Interview: Low-Power Design and Verification using CPF

September 12, 2007, Milind Padhye - Freescale Semiconductor

Milind describes some of the challenges of designing and verifying low-power ICs, as well as how CPF can be used to drive the verification processRead more »
Interview: New SoC Functional Verification Kit Kicks it up a Notch

August 30, 2007, Amjad Qureshi - Cadence Design Systems

Chip re-spins are very costly in terms of time and dollars. The new SoC Verification kit can help by enabling re-use, achieving functional closure, and providing automation. Read more »
Defining New Metrics in Enterprise Manager (Input Metrics)

August 29, 2007, Hamilton Carter - Cadence Design Systems

Discusses how to capture a metric that Enterprise Manage does not automatically capture.Read more »
Metric-Driven Methodology Speeds the Verification of a Complex Network Processor

August 22, 2007, Jean-Paul Lambrechts - Cisco Systems

Discusses Cisco metric-driven process-based approach for the functional verification of their FPGARead more »
Customizing and Extending Enterprise Manager Functionality (A Primer)

August 3, 2007, Hamilton Carter - Cadence Design Systems

Shows how the extensibility interface exposes parts of Enterprise Manager’s functionality as an object model so that users can customize the exposed functionality.Read more »
Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilog

July 30, 2007, Sarvana Kumar - TATA ELXSI Limited

Discusses verification reuse methodology for developing a complex protocol such as a Gigabit Ethernet.Read more »
Methods to Improve Verification Quality on the Module Level

June 15, 2007, Markus Gross - Siemens AG

Winner of the Best Paper Award in Functional Verification at CDNLive! EMEA, discusses the Siemens AG Plan-to-Closure Methodology. Read more »
UltraSPARC Processor Emulation Verification: Getting HW/SW right the first time

June 5, 2007, Jai Kumar - Sun Microsystems

Emulation steps in to take on challenges of running long directed, random self-checking and DFT diagnostics just where traditional SW simulators run out of gas.Read more »
QLogic Depends on Verification for First-time Silicon Success

May 10, 2007, Tom Paulson - QLogic

Tom Paulson, principal engineer for QLogic’s system simulation in the Switch Products Group, talked to cdnusers about his challenges, methodology, and verification process for their complex chips.Read more »
IEEE 1647-2008 standard update brings greater interoperability

April 30, 2007, Andrew Piziali - IEEE

An interview discussing the current status of the IEEE 1647-2008 standard update and the benefits to Verification designers.Read more »
Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach

March 14, 2007, Leonard Drucker - Cadence Design Systems

This paper, from DVCon 2007, presents flows and methodologies for using plan-driven verification.Read more »
Assertion-Based Coverage-Driven Verification

March 7, 2007, Chris Komar - Cadence Design Systems

This presentation discusses how assertion-based verification (ABV), along with coverage-driven verification (CDV), can be leveraged as a small step to a more efficient verification process.Read more »
Coverage Driven Methodology for Verification of SoC Hardware and Software Corner Cases

February 28, 2007, Jason Andrews - Cadence Design Systems

When software development takes place on hardware prototypes or final system hardware, creating and measuring complex corner cases is nearly impossible due to lack of visibilityRead more »
The Challenge is no longer the Design, it is the Verification

February 21, 2007, Tom Paulson - QLogic

I was brainstorming yesterday with some Verification forum moderators and I raised the idea that our challenge is no longer about the design, it's about the verification. I think the overall idea ...Read more »
Product Review: Incisive Generic Software Adapter (GSA)

February 12, 2007, Ernst Zwingenberger - El Camino GmbH

GSA extends Specman Elite to drive and monitor software in the same way that is done for hardware. With GSA software calls or internal signals can be bound to e ports like HDL signals. Read more »
Merging to Unified Pre-sil Post-sil Validation Environment

February 5, 2007, Assaf Eldan - Intel Corporation

Find out how Intel successfully uses Specman for verification of a design post-silicon. The paper presents the benefits of using coverage driven verification to enhance the quality and debuggability of projects.Read more »
DSP Sub-System: Spec to Closure

January 29, 2007, Ran Snir - CEBA

The SPEC to closure presents the verification process and flow of a sub-system from the ARCH spec stage, through methodology aspects, standalone environments and system-level verification.Read more »
UltraSPARC Processor Verification: Pet Peeves and What's so Cool about Xtreme HW!

January 15, 2007, Jai Kumar - Sun Microsystems

With reduced time-to-market and shortened product design cycles, it is now important, more than ever to get the product right the first time! This paper will discuss usage of Xtreme technology at Sun in general and in particular the role it played in verification of our latest generation CoolThreads UltraSPARC T1 processor. We were able to cut the product development cycle in roughly half. In this paper I will share my pet peeves and the cool features of the Xtreme technology.Read more »
Extending a Coverage Driven Verification Environment with Real Software

January 9, 2007, Ernst Zwingenberger - El Camino GmbH

This presentation discusses the value of extending a coverage -driven subsystem or module level verification environment using real software. The software will be executed on the host computer and embedded into a layered hardware verification environment. The software raises the level of abstraction and saves work in implementing the stimuli generation part of the test bench. On the other hand the power of coverage- driven verification methodology will be applied to the software as well. This environment, consisting of a simulated hardware subsystem and the software, executed on the host computer, is simplest to debug.Read more »


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Latest Forum Posts

RE: i am in need of URM cookbook
by stephenh
Hi Arun.I'm not aware of a cookbook for URM, but there is a new OVM user guide due to b...>

i am in need of URM cookbook
by arunnarraj
Hi all,       i am not able to find any cookbook regarding URM .can anyone tell me wher...>

RE: unpacked structure in DPI
by prasad_vc
Daniel,As suggested by Todd, you can use the "integer" for float and "longint" for doub...>

RE: unpacked structure in DPI
by zqlsi
Hi Todd,Thanks a lot for the answer! It's very helpful to me.Regards,Daniel>

RE: unpacked structure in DPI
by tmackett
The spec basically says that class cannot be put across the DPI interface - only packed...>
     
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