Low Power Zone


		Why Care About Power March 11, 2008, Yoav Levy - Cadence Design Systems A series of presentations from Cadence Low Power SeminarRead more »

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Low-Power Methodologies in a Multi-Core Networking Chip

March 05, 2008, Udupi Harisharan - Cisco Systems

Illustrates the low-power techniques applied on Cisco's ASIC to optimize the clock-tree power including clock gating, clock layout (First Encounter technology), and low-power flop circuitryRead more »

Learn to Optimize Your Low Power Design Process

January 4, 2008, Neil Hand - Cadence Design Systems

Interview summarizing a series of tutorials on low power design available to low power engineersListen »

Enabling Predictable Low Power Design and Implementation

October 23, 2007, Jack Erickson - Cadence Design Systems

This paper, presented at the SAME 2007 Forum, outlines what affects power at each level of the design and implementation processRead more »

Low Power Data Bus Encoding and Decoding Schemes

July 18, 2007, Isha Sood - Agilent Technologies International (Gurgaon)

Methodology is proposed to get rid of the extra bus line in the existing power aware encoding schemes such as Bus Invert and Bus Invert Transition Signaling. Read more »

Cadence Low-Power Methodology Kit Automates Area, Timing, and Power Exploration

May 15, 2007, An interview with Amjad Qureshi, Digital Kits Architect - Cadence Design Systems

Amjad Qureshi discusses the Low-Power Methodology Kit announced at CDNLive! EMEA. Read more »

Using First Encounter and VoltageStorm to Optimize Peak IR drop

April 11, 2007, Kevin Kelley - Cadence Design Systems

A case study that demonstrates the trade-offs between stripe width, peak IR drop, and worst case delay paths using First Encounter, VoltageStorm-PE, and CeltIC-NDC. Read more »

PSO Design Verification with IUS

March 29, 2007, Yonghao Chen - Cadence Design Systems

This presentation shows new features built into the latest version of Cadence Incisive Unified Simulator, IUS 5.83 that support functional verification of PSO design via simulation.Read more »

Structural and Formal Analysis of Power Management Design Using Conformal Low Power

March 21, 2007, Lam Ho - Texas Instruments

Power management design must address both active and leakage power. This, however, poses a significant challenge to the design verification. Read more »

Facilitating Low Power Scan Test in RTL Compiler

March 14, 2007, Sandeep Bhatia - Cadence Design Systems

During scan based manufacturing test, power dissipation becomes even more critical... Read more »

Reducing Dynamic and Leakage Power of a High Performance SoC

March 7, 2007, Tobing Soebroto - Cadence Design Systems

This paper describes the range of techniques applied in the design of a commercial wireless communications SOC... Read more »

What Every Low-power Designer Should Know about the Cadence Low-power Solution

February 21, 2007, Ankur Gupta - Cadence Design Systems

It is well established that the barrier to adopting low-power techniques lies in the impact to design and Read more »

Common Power Format - a Standard to Describe Power Architecture

February 12, 2007, Dr. Qi Wang - Cadence Design Systems

Power Forward Initiative is Cadence’s vision for future low power designs. It spreads out in all aspects of the design flow. With strong technologies in design, implementation and verification...Read more »

Using Advanced Low-power Techniques to Mitigate Headaches, an interview

January 29, 2007, Sean Huang - Omnivision

Power management is a big concern for us, whether in terms of switching power, or leakage power.Read more »

Cadence Low-Power Solution: a New Paradigm for Low-Power Design

January 29, 2007, An Interview with Dr. Chi-Ping Hsu - Corporate Vice-President, Chief Strategist, Product and Technology, Cadence

Low-power design considerations permeate throughout the entire design flow process. It is inextricable from the other aspects of completing a design such as timing closure and test. Adding a point tool does not solve the low-power design challenges. Every step of the way, there are new capabilities and methods that are required. We have just laid out the foundation for the next 5-10 years of innovation in the industry.Read more »

Podcast: Low-power design for big digital chips gets easier with Common Power Format

January 29, 2007, Neil Hand - Cadence

Increasing use of mobile devices as well as increasing power density of complex SoC's have made low-power a hot topic in the industry, and created headaches for design teams and their managers. In this interview, Neil Hand, Vertical Solutions, Cadence, discusses the challenges and tradeoffs for the design team, and a unique low-power solution that includes a new approach to power, from architecture through logic design, physical implementation and device signoff, with verification through-out the entire flow.Listen »

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