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Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems

April 29, 2008, Keith Felton - Cadence Design Systems

Today’s designs require flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments.Read more »

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Challenges in Implementing DDR3 Memory Interface on PCB Systems

March 11, 2008, Phil Murray - Altera Corporation

Covers modeling, simulation, and physical layout approaches required to meet JEDEC-defined termination and tight timing requirments for designing DDR3 memory interfaces on PCB systemsRead more »
Using mm.pl to Create DML MacroModels for Use in Channel Analysis

February 27, 2008, Andy Haas - Cadence Design Systems

An updated appnote/tutorial with example models and ready-to-simulate topologies.Includes compatibility with additional buffer types and document revisions for SPB16.01Read more »
Cadence Signal Integrity for Double Data Rate Interface

February 12, 2008, Prithi Ramakrishnan - Motorola

Discusses the use of Allegro PCB SI in the design and analysis of a processor-memory interface in one of Motorola's products.Read more »
A Fresh Approach to Serdes I/O Modeling

February 7, 2008, Hemant Shah - Cadence Design Systems

Discusses the need for algorithmic models, the interoperability problem, the need for IBIS BIRD 104 and the benefits systems companies and SERDES IP companies will derive from this new approachRead more »
Webinar: Using Cadence Allegro PCB SI GXL to make your Multi-GHz Serial Link Work Right out of the Box

December 21, 2007, Donald Telian - Consultant

Webinar: first in a series of webinars for PCB Designers featuring presentations from CDNLive!Read more »
Cadence Allegro Editor (v15.7) - Allegro Top 30 - Did You Know

November 16, 2007, Vincent Di Lello - Kaleidescape, Inc

This CDNLive! SV2007 People's Choice Award for SPB, provides a collection of (30) time-saving tips, tricks, and obscure functions for Cadence Allegor Editor.Read more »
Signal Integrity and PCB Layout Considerations for DDR2-800 Mb/s and DDR3 Memory Systems

October 3, 2007, Dr. Syed Bokhari - Fidus Systems, Inc

This CDNLive! SV2007 People's Choice Award for SPB, addresses signal and power integrity requirements of PCBs containing Double Data Rate (DDR) memories.Read more »
Allegro 16.0 Constraints: Effective Use and 15.x Migration Tips

September 18, 2007, John Schiavone - Cadence Design Systems

Learn how a real-world design is constrained in Allegro 16.0. Customer design was created in Allegro 15.x then constraints re-applied in the v16.0 hierarchical system.Read more »
Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation

July 18, 2007, Taranjit Kukal - Cadence Design Systems

SiP16.0 release extends the RFSiP Implementation flow offered in 15.7 to Parasitics/Simulation flow. This cdnusers interview briefly discusses the most important features.Read more »
How to use SPB 15.7 to Simplify your DDR Constraints

June 12, 2007, Mike Veal - IBM Storage

Winner of the Best Paper Award in SPB from CDNLive! EMEA, Mke Veal explores what constraints are needed in a multi-drop DDR bus.Read more »
Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2

June 7, 2007, Raj Mahajan - Virage Logic

This paper from DesignCon 2007 reviews the new DDR3 features and compares and contrasts them to previous features available in the DDR2 specification.Read more »
Signals on Serial Links: Now you see ‘em, now you don’t. What can we do?

May 29, 2007, Donald Telian - Consultant

A DesignCon2007 panel discussed the problem of un-measurable signals on next-generation serial links. Following are Donald Telian's observations from the showRead more »
Cisco’s Michael Umina Tests New PCB Global Routing Technology

May 15, 2007, Michael Umina - Cisco Systems

Michael Umina discusses his initial work with the soon-to-be released Global Route Environment Technology for Allegro PCB design.Read more »
Designing-in DDR2 Memories on PCBs using Allegro PCB SI 15.7

May 8, 2007, Kai Keskinen - Celestica

cdnusers asked Engineering Manager Kai Keskinen to talk to us about how he uses Allegro PCB SI 15.7 to design-in DDR2 memories.Read more »
Integrating Thermal Analysis with Front to Back Process

April 30, 2007, Ron Dallas - Teradyne

Shows a methodology for doing thermal analysis of circuit boards, both pre and post layout, in a collaborative design flow.Read more »
Case study of PCI Express Design Simulation using IBIS 4.1

April 25 2007, Nirmal Jain - Rambus

New modeling techniques available in the IBIS 4.1 specification allow for new standard techniques to represent multi-gigabit IO without requiring transistor-level or AMS modeling components.Read more »
Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)

April 13, 2007, Dr. Cathy Ye Liu - LSI Logic

This DesignCon 2007 paper compares performance of a variety of signaling and equalization schemes in the SerDes system at speeds of 6Gbps, 10Gbps and higherRead more »
Cadence Architects Rethink PCB Routing to Develop a Next-generation Solution

April 9, 2007, Paul Musto - Cadence Design Systems

Global Route Environment was six years in the making. Paul Musto tells how his team formed in 2001 to fundamentally change the way PCB routing is done today.Read more »
Global Route Environment: Routing at the Abstract Level

March 26, 2007, Woody Woodward - Cadence Design Systems

Global Route Environment, unveiled on March 26, allows designers to abstract their routing problem through the use of connection bundlesRead more »
PTF Manager: Rules-Driven PTF Generation and Management

March 14, 2007, Chris Day - Motorola

The PTF Manager uses classification-based rules to synthesize PTF data for use in the component selection process and by other downstream processes. Data change is managed in the Component Information System (CIS)...Read more »
Performing SSN Analysis in Early Design Stage within Allegro Package SI Environment

March 7, 2007, Charlie Shih - Cadence Design Systems

The trend now is to perform SSN analysis at early design stage to prevent SSN problems later. One approach: simulation exploration between chip and packageRead more »
Targeting Footprint Selection by Technology in the Allegro PCB Editor

February 28, 2007, Ed Lutz - Motorola

Today, a PCB designer must navigate through the available footprints and make a determination about which should be used. This can be tedious, error prone... Read more »
Initial Time Delay Issue in IBIS VT Curves

February 12, 2007, Lance Wang - Cadence Design Systems

This article, presented at the IBIS Summit at DesignCon 2007, discusses when buffers contain a long initial delay, the IBIS model might have a different behavior... Read more »
Using Modules in Allegro PCB Editor: Design Reuse for Performance

February 5, 2007, George Patrick - Tektronix

This paper will cover the physical process of creating high-speed modules and utilizing them in Allegro PCB Editor, including problems encountered with the process, solutions to overcome them, and a list of 'do's and don'ts' to aid PCB layout designers.Read more »
Using mm.pl to Create DML MacroModels for Use in Channel Analysis

January 29, 2007, Andy Haas - Cadence

Channel Analysis requires that differential drivers and receivers be in the form of an 8-terminal DML macromodel. This Perl script generates such a model...Read more »
Resolving the Critical Link: Modeling and Simulation of Complex, High-speed IC Packages

January 12, 2007, Dr. An-Yu Kuo - Optimal Corporation

Modeling a Package faces two challenges in modern high-speed designs: structure complexity and signal speed. To describe a complicated Package structure, true three dimensional (3D) representation is needed. To describe Package behavior that transfers data at the rates of multi-Gbps, complete electromagnetic field solution is required. This paper clarifies that using one type of field solver for all high-speed Package designs is not optimal opposing to a common belief that a 3D full-wave solution is all that is needed to solve any Package design problems. It then discusses why both quasi-static and full-wave 3D field solvers are necessary to solve model extraction problem for today's high-speed Packages.Read more »
Design Reuse – Subdesigns and Modules in a Complex Hierarchical Design - Allegro Design Entry HDL 15.5

January 12, 2007, Harry Bartley - Tektronix

This paper covers the schematic portion of Design Reuse. This paper shows a case study of a recent project at Tektronix, Inc. that made extensive use of subdesigns and associated modules to save time and increase the functionality of the product. The subdesign of one channel was reused to create multiple channels of the product that were virtually identical and interchangeable. This session presents the Design Reuse process as currently implemented at Tektronix.Read more »

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