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|  A Fresh Approach to Serdes I/O ModelingFebruary 7, 2008, Hemant Shah - Cadence Design SystemsDiscusses the need for algorithmic models, the interoperability problem, the need for IBIS BIRD 104 and the benefits systems companies and SERDES IP companies will derive from this new approachRead more » Interview: Making Reliable Models for SSTA September 10, 2007, Prashant Maniar, - Stratosphere Solutions, IncPrashant Manier believes the current methodology of process characterization at 45 nm , modeling and STA, is not a good predictor of performance in the presence of variability. This interview explores lower node design methodology.Read more » Interview: 45 nm and Below: Analyzing New DimensionsSeptember 10, 2007, Vassilios Gerousis - Cadence Design SystemsAs designers and process engineers delve into 45 nm process technology, they find the landscape more unforgiving than ever, margins of error tighter. Vassilios Gerousis talks about what’s going on at the 45-nm level.
Read more » Interview: Logic designers expand horizonsJuly 19, 2007, Nimish Modi - Cadence Design SystemsInterview describing the Cadence Logic Design Team Solution—a cross-divisional effort that covers all of the technologies from the Encounter and Incisive platforms relevant to logic designRead more » Interview: Logic Designers Get PhysicalJuly 9, 2007, Matt Rardon - Cadence Design SystemsMatt Rardon discusses physical predictability and how the Cadence Logic Design Team Solution closes the gap between logical and physical views of a design.Read more » Video Podcast: Cadence Entertains
Logic Designers at DACJune 26, 2007, Podcast - Cadence Design SystemsThe Design Automation Conference was held in San Diego recently, and Cadence hosted a very cool event at the San Diego Automotive Museum one evening. Surrounded by classic cars from all eras, logic designers enjoyed great food and drink, caught up with colleagues, met with Cadence Logic Design experts, and saw the latest in the Cadence Logic Design Team Solution. And one lucky person drove away in a brand new Ford Mustang. This video podcast gives you a glimpse of the action at the Cadence: Driving Innovation event. Read more » CDB to OA—The Migration ReportJune 13, 2007, Gernot Heiling - austriamicrosystemsWinner of the Custom IC Best Paper Award at CDNLive! EMEA, this presentation details the challenges and pitfalls faced during migration from ODB to OA.Read more » Video Podcast: CDNLive! EMEA
Conference recapMay 31, 2007, Podcast - Cadence Design SystemsCDNLive! EMEA recently concluded in Munich, Germany. It's part of the Cadence Design Systems series of worldwide conferences designed to bring technology users together to share ideas and tackle complex issues, both with peers and with Cadence technologists—and to mix in a little fun as well. In this podcast we hear a variety of viewpoints on the conference itself, we get highlights of product announcements made at CDNLive!, and we focus in on the EMEA geography that was a big part of CDNLive! Munich.Read more » Video Podcast: CDNLive! EMEA
Cadence CEO Mike FisterMay 23, 2007, Mike Fister - Cadence Design SystemsWe catch up with Cadence CEO Mike Fister at CDNLive! EMEA recently concluded conference in Munich, and get his views on issues ranging from the nature of CDNLive! to the special challenges facing electronics designers and manufacturers in the Europe-Middle East-Africa geography.Read more » Cadence Low-Power Methodology Kit Automates Area, Timing, and Power ExplorationMay 15, 2007, Amjad Qureshi - Cadence Design SystemsAt CDNLive! EMEA 2007, Cadence introduced its Low-Power Methodology Kit. cdnusers interviewed the Low-Power Methodology Kit architect Amjad Qureshi to find out what the Kit contains, how it works, what it does for designers, and why this Kit is important to designers facing the complex challenges of low power design.Read more » Cisco's Michael Umina Tests New PCB Global Routing TechnologyMay 15, 2007, Michael Umina - Cisco Systems The Cadence Designer Network user community recently talked with Michael Umina, ECAD Applications Engineer, at Cisco’s New England Development Center, about his initial work with the soon-to-be released Global Route Environment Technology for Allegro PCB design. Michael, who has been with Cisco for 9 years, has over 17 years experience designing PCBs.Read more » Disinherited ConnectionsApril 30, 2007, James Roberts - QualcommExplores the next level of multi-rail methodology, doing away with netSet properties and reverting back to explicit pin connections; yet retaining the transparency and automation which inherited connections offered.Read more » A Modular PDK Regression Testing SystemMarch 29 2007, Andy Weilert - Avago Technologies Brute-force regression testing involves manual interactions with the design kit and visual inspection of the resulting data -- a tedious and error-prone process. Some PDK developers have automated tests...Read more » Assertion-Based Coverage-Driven Verification March 12, 2007, Chris Komar - Cadence Design Systems This presentation discusses how assertion-based verification (ABV), along with coverage-driven verification (CDV), can be leveraged as a small step to a more efficient verification process.Read more » The Challenge is no longer the Design, it is the VerificationFebruary 21, 2007, Tom Paulson - QLogic I was brainstorming yesterday with some Verification forum moderators and I raised the idea that our challenge is no longer about the design, it's about the verification. I think the overall idea I was attempting to get to was something I think is happening to design projects, and I know it is happening to ours...Read more » Using Advanced Low-power Techniques to Mitigate HeadachesJanuary 29, 2007, An interview with Sean Huang - OmnivisionPower management is a big concern for us, whether in terms of switching power, or leakage power. Multiple supply voltage and clock-gating will help our chip to save dynamic power during operating mode; PSO and High-vt cells will reduce leakage current in our chip during stand-by mode.Read more » Cadence Low-Power Solution: a New Paradigm for Low-Power DesignJanuary 29, 2007, An Interview with Dr. Chi-Ping Hsu - Corporate Vice-President, Chief Strategist, Product and Technology, CadenceLow-power design considerations permeate throughout the entire design flow process. It is inextricable from the other aspects of completing a design such as timing closure and test. Adding a point tool does not solve the low-power design challenges. Every step of the way, there are new capabilities and methods that are required. We have just laid out the foundation for the next 5-10 years of innovation in the industry.Read more » Podcast: Low-power Design for Big Digital Chips Gets Easier with Common Power FormatJanuary 29, 2007, Neil Hand - CadenceIncreasing use of mobile devices as well as increasing power density of complex SoC's have made low-power a hot topic in the industry, and created headaches for design teams and their managers. In this interview, Neil Hand, Vertical Solutions, Cadence, discusses the challenges and tradeoffs for the design team, and a unique low-power solution that includes a new approach to power, from architecture through logic design, physical implementation and device signoff, with verification through-out the entire flow.Listen » Resolving the Critical Link: Modeling and Simulation of Complex, High-Speed IC PackagesJanuary 15, 2007, An-Yu Kuo - Optimal CorporationAs data rates achieve multi-Gigabit levels, interconnect plays a commanding role. Not only on signal transmission from ICs to boards through Packages, but also on power delivery from voltage regulation module on boards to ICs via the Package. Therefore, the Package now becomes a bottleneck on signal and power paths. Their behavior affects signal quality and the efficiency and stability of power supply. To optimize in performance and cost, Package structures have to be properly modeled, extracted and simulated with the rest of the circuit on signal and power delivery paths.Read more » A different approach to structured ASICJanuary 9, 2007, Michael Sydow - LightspeedSystem integration onto a single device and short consumer device lifecycles have forced an increasing number of difficult, yet critical, decisions on development organizations. Further complicating the design task, teams also are confronted with increased deep sub-micron technology challenges, while they also must be sensitive to the cost and risk of development of the product. This makes it more critical than ever to accurately predict and deliver the specific product features to address target market segments.Read more » | |
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