CDNLive! Silicon Valley 2006 was a huge success
Message from Michael Catrambone
Chair, Cadence Designer Network Steering Committee

Welcome to this edition of the Cadence Designer Network newsletter. I would like to follow up with everyone on our latest success with the 2nd Annual CDNLive! Silicon Valley Technical Conference held at the San Jose Convention Center. At this year's event we had over 525 Cadence customers from 180 different companies spanning 16 different countries. The larger footprint of the San Jose Convention Center allowed us to expand our networking areas like Canvas Conversations, where attendees viewed presentations and chatted with authors of some of the highest quality conference paper submissions, and Networking Live!, where attendees along with Cadence R&D met between and after sessions concluded for the day to discuss their latest design challenges and how they over came them using Cadence software. View conference highlights.

Of course the biggest success of the conference is the amount of great technical content that was presented by the Cadence user community and Cadence R&D followed by nightly events like Designer Expo, where attendees met with over 33 different EDA Exhibitors and attended Cadence Technology Night to sit in on demos of the latest Cadence technologies, new products, tool enhancements, etc. These nightly events also turned into a major networking session between attendees and Cadence R&D.

The CDNlive! India conference was held last week with similar high quality presentations, great networking, and record breaking attendance.

I also want to remind the international community members of the CDNlive! events coming up in Taiwan, China and Japan. Find more information on these events at http://www.cadence.com/cdnlive.

I would like to take this opportunity to thank all that attended, presented, and supported the Silicon Valley and Bangladesh conferences which contributed to their success. The Steering Committee and I are in the early planning stages of next years conferences and we are looking forward to see you all again at your CDNlive! location.

Sincerely,

Michael Catrambone
UTStarcom, Inc.
Chairman
Cadence Designer Network

Most Popular Articles Q3
	Interview: Comments on the Design-in IP for DDR2 memory Interfaces Dr. Sogo Hsu, Foxconn
	An Introduction to Aspect Oriented Programming in 'e' David Robinson, Verilab
	CDN User's Group Interview on DDR2 Randy Wolff, Micron Technology
	Design of a 400MHZ DDR2 Memory Controller for a High-performance CPU Application Warren Miller, Ingot Systems
	Effective Modeling and Analysis of EMI Effects on Printed Circuit Boards Kun Zhang, Huawei
	Interview: Virtuoso Platform IC 6.1 product launch Akshat Shaw, Cadence
	Thngs You Can Learn from an IBIS Model Todd Westerhoff, Cisco Systems
	System Verilog Workshop Tutorial from DVCon Tim Pylant, Cadence
	Evaluation of a New SiP Design Flow Dave Reidner, Freescale
	Designing Out DFM Issues at 65 nm Sarah Lamont, S3
	Why is My Customer a Better Verification Engineer than Me Alfonso Iniguez, Freescale
	Customization Techniques for the Allegro PCB Editor Frank Farmar, Cadence
	Interview: Xtreme III Product Launch Ping-Sheng Tseng, Cadence
	Power Grid Analysis of Low Power Designs with Coarse/Fine Grain Power Gates Mohammad Sadeghi, Cadence
	Managing a Coverage Driven Verification Program Akiva Michelson, Ace Verification
	Spice in the Unified Analog Import Tool Vivek Astvansh, Cadence
	An Analog Mixed-signal Verification Kit for Verification of Analog-Digital circuits Monia Chiavacci, Yogitech
	A Systematic Transaction-level Modeling and Verification Dr. Junhyung Um, Samsung
	SigXplorer Batch Mode Simulations Lance Wang, Cadence
	Verification Planning to Functional Closure of Processor-based SoCs Andrew Piziali, Cadence
	Custom Netlist Procedures in AMS Designer Chandrashekar Chetput, Cadence
	Tackling Design for Test Challenges in Low-Power Design Chris Hawkins, ARM
	Leveraging Assertions in System Verilog Testbench to get to Closure Tim Pylant, Cadence
	Using Hspice as the Simulation Engine Under Allegro PCB SI Cadence