Message from Michael Catrambone
Chair, Cadence Designer Network Steering Committee

CDNLive! 2006 worldwide events break all records

Welcome to the Cadence Designer Network Newsletter. After a very successful inaugural 2005 conference year, we did not disappoint with our worldwide CDNLive! conferences in 2006. Our focus is to bring Cadence® technology users together to exchange ideas and solutions through live presentations, networking opportunities, and techtorials. In 2006, we accomplished this goal with record-breaking attendance of more than 3,200 attendees at 7 locations around the world-a 30+% increase over 2005. Survey results were extremely positive, with 98% of respondents indicating they would attend again.

I would like to personally thank everyone who attended, presented, and supported the 2006 CDNLive! conferences. Your participation strongly contributed to their success.

I am looking forward to the 2007 conference year. We have opened the Call for Papers for CDNLive! EMEA, which will be held in Munich, Germany in May. The Steering Committee is finalizing paper topics for CDNLive! Silicon Valley and will announce the Call for Papers shortly.

Please check the website for more information on CDNLive! events at http://www.cadence.com/cdnlive.

Sincerely,

Michael Catrambone
UTStarcom, Inc.
Chairman
Cadence Designer Network

Most Popular Articles 2006
Most Viewed Interviews
	Challenges for Designing with DDR2 Dr. Sogo Hsu, Foxconn, Taiwan
	Resolving EMI Problems with Good Power Delivery Systems Kun Zhang, Huawei Technologies
	AC Stability Analysis for Closed-Loop Systems Momchil Milev, Texas Instruments
	Virtuoso® Platform EC6.1 Product Launch Akshat Shah, Cadence Design Systems
	ESL - Bridging the Gap Between Design and Architectural Development Mark Barry, Silicon and Software Systems
	Meeting the Challenges of Design Flow Process Jon Haldorson, PMC Sierra
Most Viewed Product Reviews
	Virtuoso UltraSim FastSPICE Simulator Tim Hersh, Atmel Corporation
	Encounter® Conformal® technology Lucie Nechanika, Freescale
	Allegro® PCB SI Dirgha Khatri, Micron Technology
	Incisive® Enterprise Manager Dr. Carsten Hoff, Advanced Driver Information
Most Viewed Technical Papers
	An Introduction to Aspect-Oriented Programming in "e" David Robinson, Verilab
	SystemVerilog Workshop Tutorial from DVCon 2006 Tim Pylant, Cadence Design Systems
	Code and Functional Coverage Tutorial Dr. Shmuel Ur, IBM
	Things You Can Learn from an IBIS Model Todd Westerhoff, Cisco Systems
	S-Parameter Correlation of Typical PCB Interconnect Structures Tan Tran, Intel
	Effective Modeling and Analysis of EMI Effects on Printed Circuit Boards Kun Zhang, Huawei Technologies
	S-Parameter Model Generation from Physical Layout using Allegro PCB SI GXL Ken Willis, Cadence Design Systems
	Evaluation of a New SiP Design Flow Dave Riedner, Freescale
	Design of a 400MHZ DDR2 Memory Controller for a High-Performance CPU Application Raghavan Menon, Ingot Systems
	Leakage Power Optimization Flow Gurudev Sirsi, Cadence Design Systems
	A Tool and Methodology for AC-Stability Analysis of Continuous-Time, Closed-Loop Systems Rod Burt, Texas Instruments
	A Pcells Library and Routing Tool Giving Designers the Option of a DFM Approach Giovanni Bertoglio, ST Microelectronics
Most Viewed Podcasts
	Mike Fister Interview on New Technology Announcements
	Jim Kahle, IBM: CDNLive! Keynote: Collaborative Innovation - Designing in the Broadband Era
	Jim Kahle, Mike Fister: Collaborative Innovation Powers Sony PS3