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CDNLive! 2007 Silicon Valley
Call for Papers now open

It's that time of year again to invite the entire Cadence® user community to consider presenting a paper at CDNLive! Silicon Valley in San Jose, CA, September 10-12. Based on the success of—and your feedback from—last year's event, the Steering Committee has developed a baseline conference schedule and generated a list of paper topics. The Call for Papers is open now. We welcome papers from Cadence technology users, as well as the talented Cadence R&D teams, in all design areas.

CDNLive! sessions are frequently a mutual exchange between speakers and attendees to validate innovative solutions to today's design challenges. Session Q&As and the many follow-up hallway conversations further contribute to the overall benefit to attendees. We constantly hear debates and rethinking of design processes based on these sessions. As a presenter myself, I know how exciting it is to see attendees' reactions to the papers, and to return to work with fresh ideas and apply new techniques.

Sincerely,

Michael Catrambone
Chair, Cadence Designer Network Steering Committee
UTStarcom, Inc.

Most Viewed Interviews
	Advanced low-power techniques to mitigate headaches Sean Huang, Omnivision
	Virtuoso® Platform EC6.1 Product Launch Akshat Shah, Cadence Design Systems
	Challenges for Designing with DDR2 Dr. Sogo Hsu, Foxconn, Taiwan
	Cadence Low-Power Solution: a New Paradigm for Low-Power Design Dr. Chi-Ping Hsu, Cadence
	Using X2Y® Multi-pin Capacitors When Designing Power Delivery Systems Steve Weir, Teraspeed
Most Popular Articles
	SystemVerilog Assertions (SVA), EZ-start Guide Chris Komar, Cadence Design Systems
	Constrained Random Data Generation Using SystemVerilog Tim Pylant, Cadence Design Systems
	SystemC TLM for Complex IP's Verification Laurent Ducousso, ST
	Resolving EMI Problems with Good Power Delivery Strategy Kun Zhang, Huawei Technologies
	Implications of a Configuration Based Verification Environment Tom Sheffler, Rambus
	Network-on-Chip: The Future of SoC Power Management Dr. Philippe Martin, Arteris
	Using Correct Timing Martin Spohr, NEC
	Modeling for Stimulus Generation, EZ-start Guide Sharon Rosenberg, Cadence
	Extending a Coverage Driven Verification Environment with Real Software Ernst Zwingenberger, El Camino GmbH
	Design and Simulation of Analog Baseband Processors Example: Analog LDPC Decoder Matthias Moerz, Aspien GmbH
Most Viewed Podcasts
	CDNLive! interview: Mike Fister on new technology announcements
	Neil Hand, Cadence Low-power Design for Big Digital Chips gets Easier with Common Power Format

February 2007

CDNLive! 2007 Gets Underway
CDNLive! 2007 worldwide schedule is available »

CDNLive! Silicon Valley
Call for Papers is now open »

CDNLive! EMEA
Registration is now open »

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