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Message from Michael Catrambone
Chair, Cadence Designer Network Steering Committee

Welcome to the Cadence Designer Network User Community. Our goal is to promote a greater exchange of technical information and ideas among customers, and between customers and Cadence throughout the year between the annual CDNLive! Conferences. The community site and CDNLive! Events worldwide are hosted by Cadence with content driven by a customer Steering Committee, Forum moderators and the community membership. The community forum commentary are posted immediately to the site with customer moderation. We will soon be rolling out survey functionality to gather the top issues from the user community and provide this information back to Cadence as input into their tool planning/development process.

I encourage everyone to take part in this new venture and connect with other Cadence users to solve problems, to share ideas and best-known methods, and to share expertise with the design community.

Congratulations Shyamkumar Thoziyoor, winner of the first “posting” contest
New contest beginning May 1 – post to a forum and you are automatically entered into the contest for an iPOD

CDNLive! update
Submit Abstracts now for Silicon Valley, deadline April 28

2006 dates and locations

Nice, France – June 25-26

Silicon Valley – Sept 12-14

Bangalore, India – October 10

Yokohama, Japan – October 19-20

Hsinchu, Taiwan – November 7

Beijing, China – November 9

Israel – November 14

Have you voted?
Be heard! Respond to the Insta-poll for your technology zone.

• Custom IC
• Digital IC
• Functional Verification
• SPB

Watch for additional surveys on
“Top Design Challenges” coming soon.

Product Reviews
Custom IC
	Virtuoso UltraSim Full Chip Simulator Tim Hersh, Atmel Corporation
	Virtuoso NeoCircuit Anders Ihlstrom, Conexant, Inc.
Digital IC
	Encounter RTL Compiler Karl W. Pfalzer, ATI Research
	Encounter Conformal Lucie Nechanicka, Freescale Semiconductor
Functional Verification
	Incisive Formal Verifier Raimund Soenning, Micronas GmbH
	Incisive Enterprise Manager Dr. Carsten Hoff, Advanced Driver Information Technology GmbH
Silicon-package-board
	Allegro PCB Router David Price, DFM
	Allegro Package SI Sachin Agrawal, Infineon Technology Pvt. Ltd.

Most Viewed Articles & Papers
Custom IC
	Creating IBIS Models using Analog Design Environment and Allegro PCB SI Model Integrity Brian Hirusana, Cadence
	Design and Verification of Nanometer SoCs Using AMS Designer Daire Breathnach, Silicon and Software Systems (S3)
	A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems Rod Burt, Texas Instruments
	A Pcells Library and Routing Tool giving Designers the Option of a DFM Approach Giovanni Bertoglio, ST Microelectronics
Digital IC
	Tackling Design for Test Challenges in Low-Power Design Chris Hawkins, ARM, Inc.
	Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning Herve Menager, Philips Semiconductor
	Logic Equivalence Checking has Arrived for FPGA Developers William McDonald and Janny Liao, Teradyne Semiconductor Test Division
	Leakage Power Optimization Flow Gurudev Bhat Sirsi, Cadence Design Systems, Inc.
	‘Fearless partitioning”: An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SoC Herve Menager, Philips Semiconductor
Functional Verification
	Managing a Coverage Driven Verification Program Akiva Michelson, Ace Verification
	Integration of PCI_Express eVC in ASIC Junjie Wang, Agilent Technologies
	Coverage Driven Verification of IEEE P1500-compliant Embedded Core Test Infrastructures Thanasis Oikonomou, Iraklis Diamantidis, Stylianos Diamantidis, Globetech Solutions
	Verification Planning to Functional Closure of Processor-based SoCs Andrew Piziali, Cadence Design Systems, Inc.
Silicon-package-board
	S-Parameter Model Generation from Physical Layout using Allegro PCB SI 630 Ken Willis, Cadence
	Creating IBIS Models using PSpice and Allegro PCB SI Model Integrity Brian Hirusana, Cadence
	Resolving EMI Problems with Good Power Delivery Strategy Kun Zhang, Huawei Technologies Co
	Evaluation of a new SiP Design Flow Dave Riedner, Freescale Semiconductor
	S-Parameter Correlation of Typical PCB Interconnect Structures Tan Tran, Intel and Donald Telian

Most Active Forum Threads
•	Digital IC, Synthesis and Test: Properly optimizing enable to clock gating enable
•	Custom IC, AMS Design and Verification: Problem in Wavescan for spectrum display in dB
•	Verification, SystemVerilog: System verilog and System C
•	Verification, e : How to use Scoreboard across environment instances
•	SPB,PCBDesign: slots in 15.2
•	SPB, Shared Code SKILL: Skill code to move component

Posts Needing Replies
•	Digital IC, Low Power: Designing for low-power
•	Digital IC, Signal Integrity: Statistical Timing Analysis
•	Custom IC, High-Frequency Design: Design Technologies
•	Verification, Formal Analysis: Which Assertion Language to Use?
•	Verification, Verification Planning: In what aspects is verification different from design?
•	SPB, Signal Integrity: Running SigXplorer in Batch Mode
•	SPB, Modeling: berkeley spice to dml

©2006 Cadence Design Systems, Inc. All rights reserved.

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